In this document one can find schematic topology and architecture of 2D_GEM Sensor Board which was used for test at FANL.
In this document one can find complete schematic topology and block diagrams for 2D_GEM Readout Control Unit which was used in test run at FANL.
In this document one can find complete schematic topology and hardware architecture for APV Module which was used for test of 2D_GEM at FANL.
Document "APV Motherboard Design" for FGT April's meeting at IUCF on April 24, 2008.
APV_MODULE is PCB where on top of APV_BOARD is bond with epoxy glue SIG_BOARD
FEE Design
In this document one can find GERBER files for Charge Sharing 2D_Readout module. This module will be used for test and study charge sharing effect in GEM detectors. All other components for assembling of this charge sharing setup we will use from old GEM detectors which we used for test purposes at FANL last year.
NOTE: Files in "TSTBOARD.zip" are possible open with P-CAD2004 software tool and file "tstboard.pdf" is "pdf" accessible file where one can see architecture of mentioned unit.
This document was requested by Dave Underwood and Gerrard Visser for they purposes to compare they design with GEM/FANL prototype buildup at MIT/Bates Linear Accelerator.
In attached document is multipurpose module with which one can test all mechanical and connectivity features.
In this document one can find VHDL Programs and State Machines for 2D_GEM Control Unit which was engaged in readout process from GEM detector at FANL.
drawings showing the final dimensions of the WSC and the GEM quarter section frames,
8-19-2009, Jason Bessuille
These are the official drawings and documentation used for fabrication of the FGT Front End Electronics hardware. We will try to maintain this page up-to-date with any revisions.
To view design files, download the Altium Viewer (no cost).
FGT Readout Module (FRM)
Terminator Board
Interconnect Board
High Voltage Board
