APV Readout System Long Cable Test Setup

The APV front-end ASIC which forms the core of the Forward GEM Tracker readout system combines a sensitive preamplifier, switched-capacitor analog memory array, and low-voltage differential analog output buffer.

Operating such an ASIC directly over a long cable, with the analog output digitized at the far end of the cable, potentially presents some challenges. Of course, there are are also opportunities, to minimize the power dissipation inside the inner field cage region, minimize dead materials, and to maximize reliability by placing most of the electronics in an easily serviceable location on the STAR electronics platform.

At IUCF we are constructing a pair of test boards, one which models the APV readout module "ARM", the other which models the APV cable connector board.

Besides testing the performance of the MIT APV motherboards with a long cable interface, this set of test boards is important to:

  • Develop the interface definitions between the IUCF "ARM" and the MIT "APV Motherboard"
  • Demonstrate a low-dropout low-voltage regulator for the APV power, and characterize its performance
  • Demonstrate the control of APV chips and an I2C temperature sensor via the UART - I2C bridge chip
  • Evaluate the effects of various thermal and grounding options for the FGT
  • Run the APV's for detector testing (either with an external ADC and clock source, or with the connector board here and the full ARM to be developed

Here are the design files:

The connector board should be compatible with a pair of FGT APV Motherboards, a total of 10 APV chips. The mock readout board provides only two channels of analog line receiver, testing two different concepts for this. One is a DC coupled line receiver using Analog Devices # AD8129, the other is a transformer-coupled line receiver using a TI # OPA684 opamp. The transformer solution should have superior noise and common-mode rejection and lower power, but it is of course not DC coupled as we would wish. It could be used if DC restoration is applied digitally in the FPGA (on the real ARM).

First results:

Here is the APV readout sequence, looking good:


The "noise" which is apparent here is merely crosstalk from the clock signal, and as such will be easily removed by the filter in front of the ADC. Neither that filter nor the cable frequency equalization filter is in place for the measurement above.

Clock frequency was 40 MHz; APV was triggered at 1 kHz from a pulse generator. No inputs connected, no shield box. Cable is Belden 1424A, 110 feet, coiled up on workbench.