Status and Pedestal Tables

We used one good emc-check run with 100k events each for each fill.  Some fills did not have a good emc-check run.  Below are the runs we used.
Run List

Produced ADC distributions from raw DAQ files following the instrucitons here.

Determined the status and pedestals for each tower and mapmt channel with the instructions here.

Summary of tower issues:
On average, about 2.5% of all towers are masked-out per fill.
Tower Status by Fill

02TA01:  dead entire run
02TC04:  bad entire run
02TC06:  fail for part of the run
04TB07:  stuck bit entire run
04TC01:  fail for part of the run
05TA12:  stuck bit entire run
06TA03:  failed entire run
06TA07:  stuck bit entire run
06TC08:  dead for one run
06TD04:  failed for one run
07TC05:  failed entire run
08TB07:  stuck bit entire run
10TA09:  dead for two runs
10TC02:  failed entire run
10TC03:  failed entire run
10TC09:  failed entire run
10TC11:  good for only two runs
11TA08:  dead entire run
11TA12:  mark as stuck bit entire run
11TB08:  failed entire run
11TC04:  dead for part of the run
12TB02:  dead part of the run
12TC05:  bad entire run
12TD01:  bad for part of the run

**See attached file for MAPMT pedestal widths**