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universe.h
1 /* universe.h - VMEbus Interface Controller */
2 
3 /* Copyright, 1996-1997 Wind River Systems, Inc. */
4 /* Copyright 1996 Motorola, Inc. */
5 
6 /*
7 modification history
8 --------------------
9 01c,18feb97,mas changed VINT...SW_IACK to VINT...SW_INT per MR #39; changed
10  UNIVERSE_VME_IACK_INT to UNIVERSE_VME_SW_INT (SPR 7811).
11 01b,02jan97,dat documentation
12 01a,10jul96,rhk written.
13 */
14 
15 #ifndef INCuniverseh
16 #define INCuniverseh
17 
18 /*
19 This file contains constants for the Universe PCI-VME interface chip.
20 The macro UNIVERSE_BASE_ADRS must be defined when including this header.
21 
22 The registers are listed in ascending (numerical) order; the definitions
23 for each register are started with a header eg.
24 */
25 
26 #ifdef _ASMLANGUAGE
27 #define CASTINT
28 #else
29 #define CASTINT (unsigned int *)
30 #endif /* _ASMLANGUAGE */
31 
32 /*
33  * on-board access, register definitions
34  * these registers MUST BE WRITTEN 4-BYTE WRITES ONLY
35  * they can be read as byte, two-bytes or 4-bytes.
36  */
37 
38 #ifndef UNIVERSE_ADRS /* to permit alternative board addressing */
39 #define UNIVERSE_ADRS(reg) (CASTINT (UNIVERSE_BASE_ADRS + reg ))
40 #endif /* UNIVERSE_ADRS */
41 
42 #ifndef UNIV_BUS_ADRS /* to permit alternative board addressing */
43 #define UNIV_BUS_ADRS(reg) (CASTINT (UNIV_BUS_BASE_ADRS + (reg)))
44 #endif /* UNIV_BUS_ADRS */
45 
46 #ifndef _ASMLANGUAGE
47 
48 typedef struct
49  {
50  UINT32 *regAddr; /* Address of register */
51  UINT32 regVal; /* Value of register */
52  UINT32 regMask; /* Mask value of register */
53  } UNIVERSE_REG_TYPE;
54 
55 typedef struct
56  {
57  UINT32 pciBs; /* PCI_BS */
58  UINT32 mastCtl; /* MAST_CTL */
59  UINT32 miscCtl; /* MISC_CTL */
60  UNIVERSE_REG_TYPE pciLsi[4][4]; /* LSIx Registers */
61  } UNIVERSE_CNFG_HDR;
62 
63 #endif /*_ASMLANGUAGE*/
64 
65 /* VME interrupt level definitions */
66 
67 #define LVL0 0x0001
68 #define LVL1 0x0002
69 #define LVL2 0x0004
70 #define LVL3 0x0008
71 #define LVL4 0x0010
72 #define LVL5 0x0020
73 #define LVL6 0x0040
74 #define LVL7 0x0080
75 
76 /* additional VME interrupts supported by the UNIVERSE chip */
77 
78 #define UNIVERSE_DMA_INT 0x0100 /* bit setting for DMA intr */
79 #define UNIVERSE_LERR_INT 0x0200 /* bit setting for PCI bus err intr */
80 #define UNIVERSE_VERR_INT 0x0400 /* bit setting for VMEbus err int */
81 #define UNIVERSE_VME_SW_IACK_INT 0x1000 /* bit setting for VME SW IACK intr */
82 #define UNIVERSE_PCI_SW_INT 0x2000 /* bit setting for SW intr */
83 #define UNIVERSE_SYSFAIL_INT 0x4000 /* bit setting for SYSFAIL intr */
84 #define UNIVERSE_ACFAIL_INT 0x8000 /* bit setting for ACFAIL intr */
85 
86 #define UNIVERSE_INT_MASK 0x0000f700 /* mask for the interrupts
87  defined above */
88 
89 #define UNIVERSE_CNFG_OFFSET 0x100 /* offset VME specific part */
90 
91 /* WRITES MUST BE 4-BYTE WRITES ONLY */
92 
93 /*
94  * Device ID - Newbridge allocated device ident 0x00 31-16
95  * Vendor ID - PCI SIG allocated vendor identifier 0x00 15-00
96  */
97 
98 #define UNIVERSE_PCI_ID UNIVERSE_ADRS(0x00)
99 
100 /* PCI Configuration Space Control and Status Reg 0x00 31-00 */
101 
102 #define UNIVERSE_PCI_CSR UNIVERSE_ADRS(0x04)
103 
104 /*
105  * PCI Configuration Class Register
106  * PCI Base Class Code - "PCI bridge device" 0x10 31-24
107  * PCI Sub Class Code - "other bridge device" 0x10 23-16
108  * PCI Programming Interface - (Not Applicable) 0x10 15-08
109  * Revision ID 0x10 07-00
110  */
111 
112 #define UNIVERSE_PCI_CLASS UNIVERSE_ADRS(0x08)
113 
114 /* PCI Configuration Miscellaneous 0 Register 0x00 31-00 */
115 
116 #define UNIVERSE_PCI_MISC0 UNIVERSE_ADRS(0x0c)
117 
118 /*
119  * PCI Base Address Register 0x08 31-16
120  * PCI Bus Address Space Register 0x08 15-00
121  */
122 
123 #define UNIVERSE_PCI_BS UNIVERSE_ADRS(0x10)
124 
125 /* PCI Configuration Miscellaneous 1 Register 0x00 31-00 */
126 
127 #define UNIVERSE_PCI_MISC1 UNIVERSE_ADRS(0x3c)
128 
129 /* PCI Slave Image 0 Control Register 0x100 31-00 */
130 
131 #define UNIVERSE_LSI0_CTL UNIVERSE_ADRS(0x100)
132 
133 /*
134  * PCI Slave Image 0 Base Address Register 0x104 31-12
135  * Universe Reserved 0x104 11-00
136  */
137 
138 #define UNIVERSE_LSI0_BS UNIVERSE_ADRS(0x104)
139 
140 /*
141  * PCI Slave Image 0 Bound Address Register 0x108 31-12
142  * Universe Reserved 0x108 11-00
143  */
144 
145 #define UNIVERSE_LSI0_BD UNIVERSE_ADRS(0x108)
146 
147 /*
148  * PCI Slave Image 0 Translation Offset 0x10C 31-12
149  * Universe Reserved 0x10C 11-00
150  */
151 
152 #define UNIVERSE_LSI0_TO UNIVERSE_ADRS(0x10c)
153 
154 /* PCI Slave Image 1 Control Register 0x114 31-00 */
155 
156 #define UNIVERSE_LSI1_CTL UNIVERSE_ADRS(0x114)
157 
158 /*
159  * PCI Slave Image 1 Base Address Register 0x118 31-12
160  * Universe Reserved 0x118 11-00
161  */
162 
163 #define UNIVERSE_LSI1_BS UNIVERSE_ADRS(0x118)
164 
165 /*
166  * PCI Slave Image 1 Bound Address Register 0x11C 31-12
167  * Universe Reserved 0x11C 11-00
168  */
169 
170 #define UNIVERSE_LSI1_BD UNIVERSE_ADRS(0x11C)
171 
172 /*
173  * PCI Slave Image 1 Translation Offset 0x120 31-12
174  * Universe Reserved 0x120 11-00
175  */
176 
177 #define UNIVERSE_LSI1_TO UNIVERSE_ADRS(0x120)
178 
179 /* PCI Slave Image 2 Control Register 0x128 31-00 */
180 
181 #define UNIVERSE_LSI2_CTL UNIVERSE_ADRS(0x128)
182 
183 /*
184  * PCI Slave Image 2 Base Address Register 0x12C 31-12
185  * Universe Reserved 0x12C 11-00
186  */
187 
188 #define UNIVERSE_LSI2_BS UNIVERSE_ADRS(0x12C)
189 
190 /*
191  * PCI Slave Image 2 Bound Address Register 0x130 31-12
192  * Universe Reserved 0x130 11-00
193  */
194 
195 #define UNIVERSE_LSI2_BD UNIVERSE_ADRS(0x130)
196 
197 /*
198  * PCI Slave Image 2 Translation Offset 0x134 31-12
199  * Universe Reserved 0x134 11-00
200  */
201 
202 #define UNIVERSE_LSI2_TO UNIVERSE_ADRS(0x134)
203 
204 /* PCI Slave Image 3 Control Register 0x13C 31-00 */
205 
206 #define UNIVERSE_LSI3_CTL UNIVERSE_ADRS(0x13C)
207 
208 /*
209  * PCI Slave Image 3 Base Address Register 0x140 31-12
210  * Universe Reserved 0x140 11-00
211  */
212 
213 #define UNIVERSE_LSI3_BS UNIVERSE_ADRS(0x140)
214 
215 /*
216  * PCI Slave Image 3 Bound Address Register 0x144 31-12
217  * Universe Reserved 0x144 11-00
218  */
219 
220 #define UNIVERSE_LSI3_BD UNIVERSE_ADRS(0x144)
221 
222 /*
223  * PCI Slave Image 3 Translation Offset 0x148 31-12
224  * Universe Reserved 0x148 11-00
225  */
226 
227 #define UNIVERSE_LSI3_TO UNIVERSE_ADRS(0x148)
228 
229 /*
230  * Universe Reserved 0x170 31-02
231  * Special Cycle 0x170 01-00
232  */
233 
234 #define UNIVERSE_SCYC_CTL UNIVERSE_ADRS(0x170)
235 
236 /*
237  * Address for Special Cycle 0x174 31-02
238  * Universe Reserved 0x174 01-00
239  */
240 
241 #define UNIVERSE_SCYC_ADDR UNIVERSE_ADRS(0x174)
242 
243 /* Special Cycle Bit Enable Mask 0x178 31-00 */
244 
245 #define UNIVERSE_SCYC_EN UNIVERSE_ADRS(0x178)
246 
247 /* Special Cycle Compare Register 0x178 31-00 */
248 
249 #define UNIVERSE_SCYC_CMP UNIVERSE_ADRS(0x17c)
250 
251 /* Special Cycle Swap Register 0x178 31-00 */
252 
253 #define UNIVERSE_SCYC_SWP UNIVERSE_ADRS(0x180)
254 
255 /* Other Registers */
256 
257 #define UNIVERSE_LMISC UNIVERSE_ADRS(0x184)
258 #define UNIVERSE_SLSI UNIVERSE_ADRS(0x188)
259 #define UNIVERSE_L_CMDERR UNIVERSE_ADRS(0x18c)
260 #define UNIVERSE_LAERR UNIVERSE_ADRS(0x190)
261 #define UNIVERSE_DCTL UNIVERSE_ADRS(0x200)
262 #define UNIVERSE_DTBC UNIVERSE_ADRS(0x204)
263 #define UNIVERSE_DLA UNIVERSE_ADRS(0x208)
264 #define UNIVERSE_DVA UNIVERSE_ADRS(0x210)
265 #define UNIVERSE_DCPP UNIVERSE_ADRS(0x218)
266 #define UNIVERSE_DGCS UNIVERSE_ADRS(0x220)
267 #define UNIVERSE_D_LLUE UNIVERSE_ADRS(0x224)
268 #define UNIVERSE_LINT_EN UNIVERSE_ADRS(0x300)
269 #define UNIVERSE_LINT_STAT UNIVERSE_ADRS(0x304)
270 #define UNIVERSE_LINT_MAP0 UNIVERSE_ADRS(0x308)
271 #define UNIVERSE_LINT_MAP1 UNIVERSE_ADRS(0x30C)
272 #define UNIVERSE_VINT_EN UNIVERSE_ADRS(0x310)
273 #define UNIVERSE_VINT_STAT UNIVERSE_ADRS(0x314)
274 #define UNIVERSE_VINT_MAP0 UNIVERSE_ADRS(0x318)
275 #define UNIVERSE_VINT_MAP1 UNIVERSE_ADRS(0x31C)
276 #define UNIVERSE_STATID UNIVERSE_ADRS(0x320)
277 #define UNIVERSE_V1_STATID UNIVERSE_ADRS(0x324)
278 #define UNIVERSE_V2_STATID UNIVERSE_ADRS(0x328)
279 #define UNIVERSE_V3_STATID UNIVERSE_ADRS(0x32C)
280 #define UNIVERSE_V4_STATID UNIVERSE_ADRS(0x330)
281 #define UNIVERSE_V5_STATID UNIVERSE_ADRS(0x334)
282 #define UNIVERSE_V6_STATID UNIVERSE_ADRS(0x338)
283 #define UNIVERSE_V7_STATID UNIVERSE_ADRS(0x33C)
284 #define UNIVERSE_MAST_CTL UNIVERSE_ADRS(0x400)
285 #define UNIVERSE_MISC_CTL UNIVERSE_ADRS(0x404)
286 #define UNIVERSE_MISC_STAT UNIVERSE_ADRS(0x408)
287 #define UNIVERSE_USER_AM UNIVERSE_ADRS(0x40C)
288 #define UNIVERSE_VSI0_CTL UNIVERSE_ADRS(0xF00)
289 #define UNIVERSE_VSI0_BS UNIVERSE_ADRS(0xF04)
290 #define UNIVERSE_VSI0_BD UNIVERSE_ADRS(0xF08)
291 #define UNIVERSE_VSI0_TO UNIVERSE_ADRS(0xF0C)
292 #define UNIVERSE_VSI1_CTL UNIVERSE_ADRS(0xF14)
293 #define UNIVERSE_VSI1_BS UNIVERSE_ADRS(0xF18)
294 #define UNIVERSE_VSI1_BD UNIVERSE_ADRS(0xF1C)
295 #define UNIVERSE_VSI1_TO UNIVERSE_ADRS(0xF20)
296 #define UNIVERSE_VSI2_CTL UNIVERSE_ADRS(0xF28)
297 #define UNIVERSE_VSI2_BS UNIVERSE_ADRS(0xF2C)
298 #define UNIVERSE_VSI2_BD UNIVERSE_ADRS(0xF30)
299 #define UNIVERSE_VSI2_TO UNIVERSE_ADRS(0xF34)
300 #define UNIVERSE_VSI3_CTL UNIVERSE_ADRS(0xF3C)
301 #define UNIVERSE_VSI3_BS UNIVERSE_ADRS(0xF40)
302 #define UNIVERSE_VSI3_BD UNIVERSE_ADRS(0xF44)
303 #define UNIVERSE_VSI3_TO UNIVERSE_ADRS(0xF48)
304 #define UNIVERSE_VRAI_CTL UNIVERSE_ADRS(0xF70)
305 #define UNIVERSE_VRAI_BS UNIVERSE_ADRS(0xF74)
306 #define UNIVERSE_VCSR_CTL UNIVERSE_ADRS(0xF80)
307 #define UNIVERSE_VCSR_TO UNIVERSE_ADRS(0xF84)
308 #define UNIVERSE_V_AMERR UNIVERSE_ADRS(0xF88)
309 #define UNIVERSE_VAERR UNIVERSE_ADRS(0xF8C)
310 #define UNIVERSE_VCSR_CLR UNIVERSE_ADRS(0xFF4)
311 #define UNIVERSE_VCSR_SET UNIVERSE_ADRS(0xFF8)
312 #define UNIVERSE_VCSR_BS UNIVERSE_ADRS(0xFFC)
313 
314 /* NOW LET'S DEFINE THE BITS FOR THESE REGISTERS */
315 
316 /* PCI MISC0 Register */
317 
318 #define PCI_MISC0_LATENCY_TIMER 0x0000f800 /* max. value for timer */
319 
320 /* PCI Configuration Space Control and Status Register */
321 
322 #define PCI_CSR_MASK 0x007ffc00 /* Reserved bits */
323 #define PCI_CSR_D_PE (1 << 31) /* Detected/Clear Parity Error*/
324 #define PCI_CSR_S_SERR (1 << 30) /* Signalled SERR# */
325 #define PCI_CSR_R_MA (1 << 29) /* Received Master Abort */
326 #define PCI_CSR_R_TA (1 << 28) /* Received Target Abort */
327 #define PCI_CSR_S_TA (1 << 27) /* Signalled Target Abort */
328 #define PCI_CSR_DEVSEL_MEDIUM (1 << 25) /* Universe is medium speed */
329 #define PCI_CSR_DP_D (1 << 24) /* Master detected/generated */
330  /* a data parity error */
331 #define PCI_CSR_TFBBC (1 << 23) /* Target Fast Back to Back */
332  /* Capable (must be ?) */
333 #define PCI_CSR_MFBBC (1 << 9) /* Master Fast Back to Back */
334  /* Capable (must be 0) */
335 #define PCI_CSR_SERR_EN (1 << 8) /* Enable SERR# drivers */
336 #define PCI_CSR_WAIT (1 << 7) /* Wait Cycle Control */
337 #define PCI_CSR_PERSP (1 << 6) /* Enable Parity Error Resp */
338 #define PCI_CSR_VGAPS (1 << 5) /* VGA Palette Snp (must be 0)*/
339 #define PCI_CSR_MWI_EN (1 << 4) /* Enable Memory Write and */
340  /* Invalidate (must be 0) */
341 #define PCI_CSR_SC (1 << 3) /* Respond to Special Cycles */
342  /* (must be 0) */
343 #define PCI_CSR_BM (1 << 2) /* Master Enable */
344 #define PCI_CSR_MS (1 << 1) /* Target Memory Enable */
345 #define PCI_CSR_IOS (1) /* Target I/O Enable */
346 
347 /* PCI Slave Image Control Register 0 */
348 
349 #define LSI0_CTL_MASK 0x3f380efc /* Mask bits */
350 #define LSI0_CTL_EN (1 << 31) /* Enable PCI Slave Image */
351 #define LSI0_CTL_WP (1 << 30) /* Enable Posted Writes */
352 #define LSI0_CTL_D8 (0 << 22) /* Max VME Data Width = 8 */
353 #define LSI0_CTL_D16 (1 << 22) /* Max VME Data Width = 16 */
354 #define LSI0_CTL_D32 (2 << 22) /* Max VME Data Width = 32 */
355 #define LSI0_CTL_D64 (3 << 22) /* Max VME Data Width = 64 */
356 #define LSI0_CTL_A16 (0 << 16) /* VME Address Space A16 */
357 #define LSI0_CTL_A24 (1 << 16) /* VME Address Space A24 */
358 #define LSI0_CTL_A32 (2 << 16) /* VME Address Space A32 */
359 #define LSI0_CTL_CSR (5 << 16) /* VME Address Space CSR */
360 #define LSI0_CTL_USER1 (6 << 16) /* VME Address Space USER 1 */
361 #define LSI0_CTL_USER2 (7 << 16) /* VME Address Space USER 2 */
362 #define LSI0_CTL_PGM (1 << 14) /* Program AM Code */
363 #define LSI0_CTL_DATA (0 << 14) /* Data AM Code */
364 #define LSI0_CTL_SUP (1 << 12) /* Supervisor AM Code */
365 #define LSI0_CTL_USR (0 << 12) /* User AM Code */
366 #define LSI0_CTL_BLK (1 << 8) /* Supervisor AM Code */
367 #define LSI0_CTL_SINGLE (0 << 8) /* User AM Code */
368 #define LSI0_CTL_PCI_MEM (0 << 0) /* PCI Memory Space */
369 #define LSI0_CTL_PCI_IO (1 << 0) /* PCI I/O Space */
370 #define LSI0_CTL_PCI_CONFIG (2 << 0) /* PCI Type 1 Config Space */
371 
372 /* PCI Slave Image Base Address Register 0 */
373 
374 #define LSI0_BS_MASK 0x00000fff
375 
376 /* PCI Slave Image Bound Address Register 0 */
377 
378 #define LSI0_BD_MASK 0x00000fff
379 
380 /* PCI Slave Image Translation Offset Register 0 */
381 
382 #define LSI0_TO_MASK 0x00000fff
383 
384 /* PCI Slave Image Control Register 1 */
385 
386 #define LSI1_CTL_MASK 0x3f380efc /* Mask bits */
387 #define LSI1_CTL_EN (1 << 31) /* Enable PCI Slave Image */
388 #define LSI1_CTL_WP (1 << 30) /* Enable Posted Writes */
389 #define LSI1_CTL_D8 (0 << 22) /* Max VME Data Width = 8 */
390 #define LSI1_CTL_D16 (1 << 22) /* Max VME Data Width = 16 */
391 #define LSI1_CTL_D32 (2 << 22) /* Max VME Data Width = 32 */
392 #define LSI1_CTL_D64 (3 << 22) /* Max VME Data Width = 64 */
393 #define LSI1_CTL_A16 (0 << 16) /* VME Address Space A16 */
394 #define LSI1_CTL_A24 (1 << 16) /* VME Address Space A24 */
395 #define LSI1_CTL_A32 (2 << 16) /* VME Address Space A32 */
396 #define LSI1_CTL_CSR (5 << 16) /* VME Address Space CSR */
397 #define LSI1_CTL_USER1 (6 << 16) /* VME Address Space USER 1 */
398 #define LSI1_CTL_USER2 (7 << 16) /* VME Address Space USER 2 */
399 #define LSI1_CTL_PGM (1 << 14) /* Program AM Code */
400 #define LSI1_CTL_DATA (0 << 14) /* Data AM Code */
401 #define LSI1_CTL_SUP (1 << 12) /* Supervisor AM Code */
402 #define LSI1_CTL_USR (0 << 12) /* User AM Code */
403 #define LSI1_CTL_BLK (1 << 8) /* Supervisor AM Code */
404 #define LSI1_CTL_SINGLE (0 << 8) /* User AM Code */
405 #define LSI1_CTL_PCI_MEM (0 << 0) /* PCI Memory Space */
406 #define LSI1_CTL_PCI_IO (1 << 0) /* PCI I/O Space */
407 #define LSI1_CTL_PCI_CONFIG (2 << 0) /* PCI Type 1 Config Space */
408 
409 /* PCI Slave Image Base Address Register 1 */
410 
411 #define LSI1_BS_MASK 0x0000ffff
412 
413 /* PCI Slave Image Bound Address Register 1 */
414 
415 #define LSI1_BD_MASK 0x0000ffff
416 
417 /* PCI Slave Image Translation Offset Register 1 */
418 
419 #define LSI1_TO_MASK 0x0000ffff
420 
421 /* PCI Slave Image Control Register 2 */
422 
423 #define LSI2_CTL_MASK 0x3f380efc /* Mask bits */
424 #define LSI2_CTL_EN (1 << 31) /* Enable PCI Slave Image */
425 #define LSI2_CTL_WP (1 << 30) /* Enable Posted Writes */
426 #define LSI2_CTL_D8 (0 << 22) /* Max VME Data Width = 8 */
427 #define LSI2_CTL_D16 (1 << 22) /* Max VME Data Width = 16 */
428 #define LSI2_CTL_D32 (2 << 22) /* Max VME Data Width = 32 */
429 #define LSI2_CTL_D64 (3 << 22) /* Max VME Data Width = 64 */
430 #define LSI2_CTL_A16 (0 << 16) /* VME Address Space A16 */
431 #define LSI2_CTL_A24 (1 << 16) /* VME Address Space A24 */
432 #define LSI2_CTL_A32 (2 << 16) /* VME Address Space A32 */
433 #define LSI2_CTL_CSR (5 << 16) /* VME Address Space CSR */
434 #define LSI2_CTL_USER1 (6 << 16) /* VME Address Space USER 1 */
435 #define LSI2_CTL_USER2 (7 << 16) /* VME Address Space USER 2 */
436 #define LSI2_CTL_PGM (1 << 14) /* Program AM Code */
437 #define LSI2_CTL_DATA (0 << 14) /* Data AM Code */
438 #define LSI2_CTL_SUP (1 << 12) /* Supervisor AM Code */
439 #define LSI2_CTL_USR (0 << 12) /* User AM Code */
440 #define LSI2_CTL_BLK (1 << 8) /* Supervisor AM Code */
441 #define LSI2_CTL_SINGLE (0 << 8) /* User AM Code */
442 #define LSI2_CTL_PCI_MEM (0 << 0) /* PCI Memory Space */
443 #define LSI2_CTL_PCI_IO (1 << 0) /* PCI I/O Space */
444 #define LSI2_CTL_PCI_CONFIG (2 << 0) /* PCI Type 1 Config Space */
445 
446 /* PCI Slave Image Base Address Register 2 */
447 
448 #define LSI2_BS_MASK 0x0000ffff
449 
450 /* PCI Slave Image Bound Address Register 2 */
451 
452 #define LSI2_BD_MASK 0x0000ffff
453 
454 /* PCI Slave Image Translation Offset Register 2 */
455 
456 #define LSI2_TO_MASK 0x0000ffff
457 
458 /* PCI Slave Image Control Register 3 */
459 
460 #define LSI3_CTL_MASK 0x3f380efc /* Mask bits */
461 #define LSI3_CTL_EN (1 << 31) /* Enable PCI Slave Image */
462 #define LSI3_CTL_WP (1 << 30) /* Enable Posted Writes */
463 #define LSI3_CTL_D8 (0 << 22) /* Max VME Data Width = 8 */
464 #define LSI3_CTL_D16 (1 << 22) /* Max VME Data Width = 16 */
465 #define LSI3_CTL_D32 (2 << 22) /* Max VME Data Width = 32 */
466 #define LSI3_CTL_D64 (3 << 22) /* Max VME Data Width = 64 */
467 #define LSI3_CTL_A16 (0 << 16) /* VME Address Space A16 */
468 #define LSI3_CTL_A24 (1 << 16) /* VME Address Space A24 */
469 #define LSI3_CTL_A32 (2 << 16) /* VME Address Space A32 */
470 #define LSI3_CTL_CSR (5 << 16) /* VME Address Space CSR */
471 #define LSI3_CTL_USER1 (6 << 16) /* VME Address Space USER 1 */
472 #define LSI3_CTL_USER2 (7 << 16) /* VME Address Space USER 2 */
473 #define LSI3_CTL_PGM (1 << 14) /* Program AM Code */
474 #define LSI3_CTL_DATA (0 << 14) /* Data AM Code */
475 #define LSI3_CTL_SUP (1 << 12) /* Supervisor AM Code */
476 #define LSI3_CTL_USR (0 << 12) /* User AM Code */
477 #define LSI3_CTL_BLK (1 << 8) /* Supervisor AM Code */
478 #define LSI3_CTL_SINGLE (0 << 8) /* User AM Code */
479 #define LSI3_CTL_PCI_MEM (0 << 0) /* PCI Memory Space */
480 #define LSI3_CTL_PCI_IO (1 << 0) /* PCI I/O Space */
481 #define LSI3_CTL_PCI_CONFIG (2 << 0) /* PCI Type 1 Config Space */
482 
483 /* PCI Slave Image Base Address Register 3 */
484 
485 #define LSI3_BS_MASK 0x0000ffff
486 
487 /* PCI Slave Image Bound Address Register 3 */
488 
489 #define LSI3_BD_MASK 0x0000ffff
490 
491 /* PCI Slave Image Translation Offset Register 3 */
492 
493 #define LSI3_TO_MASK 0x0000ffff
494 
495 /* PCI Special Cycle Control Register */
496 
497 #define SCYC_CTL_MASK 0xfffffffc
498 #define SCYC_CTL_DISABLE (0) /* Disable Special Cycle Gen */
499 #define SCYC_CTL_RMW (1) /* RMW Special Cycle */
500 #define SCYC_CTL_ADO (2) /* ADO Special Cycle */
501 
502 /* PCI Special Cycle Address Register */
503 
504 #define SCYC_ADDR_MASK 0x3
505 
506 /* PCI Miscellaneous Register */
507 
508 #define LMISC_CRT_INFINITE (0 << 28) /* Coupled Request Timeout */
509 #define LMISC_CRT_128_USEC (1 << 28) /* Coupled Request Timeout */
510 #define LMISC_CRT_256_USEC (2 << 28) /* Coupled Request Timeout */
511 #define LMISC_CRT_512_USEC (3 << 28) /* Coupled Request Timeout */
512 #define LMISC_CRT_1024_USEC (4 << 28) /* Coupled Request Timeout */
513 #define LMISC_CRT_2048_USEC (5 << 28) /* Coupled Request Timeout */
514 #define LMISC_CRT_4096_USEC (6 << 28) /* Coupled Request Timeout */
515 
516 #define LMISC_CWT_DISABLE (0 << 24) /* Coupled Window Timeout */
517  /* Immediate Release after first transaction */
518 #define LMISC_CWT_16_CLKS (1 << 24) /* Coupled Window Timeout */
519 #define LMISC_CWT_32_CLKS (2 << 24) /* Coupled Window Timeout */
520 #define LMISC_CWT_64_CLKS (3 << 24) /* Coupled Window Timeout */
521 #define LMISC_CWT_128_CLKS (4 << 24) /* Coupled Window Timeout */
522 #define LMISC_CWT_256_CLKS (5 << 24) /* Coupled Window Timeout */
523 #define LMISC_CWT_512_CLKS (6 << 24) /* Coupled Window Timeout */
524 
525 /*
526  * Special PCI Slave Image
527  * - provides access to all of A16 and most of A24 VME Space
528  */
529 #define SLSI_EN (1 << 31) /* Enable PCI Slave Image */
530 #define SLSI_WP (1 << 30) /* Enable Posted Writes */
531 #define SLSI_D16 (1 << 20) /* Max VME Data Width = 16 */
532 #define SLSI_D32 (2 << 20) /* Max VME Data Width = 32 */
533 #define SLSI_PGM (1 << 12) /* Program AM Code */
534 #define SLSI_DATA (0 << 12) /* Data AM Code */
535 #define SLSI_SUP (1 << 8) /* Supervisor AM Code */
536 #define SLSI_USR (0 << 8) /* User AM Code */
537 #define SLSI_PCI_MEM (0 << 0) /* PCI Memory Space */
538 #define SLSI_PCI_IO (1 << 0) /* PCI I/O Space */
539 #define SLSI_PCI_CONFIG (2 << 0) /* PCI Type 1 Config Space */
540 
541 /* PCI Command Error Log Register */
542 
543 #define L_CMDERR_LOG (0xf << 28) /* Command Error Log */
544 #define L_CMDERR_MASK 0x078fffff /* Reserved bits */
545 #define L_CMDERR_M_ERR (1 << 27) /* Multiple Error Occurred */
546 #define L_CMDERR_L_STAT (1 << 23) /* Logs are valid and halted */
547 #define L_CMDERR_L_ENABLE (1 << 23) /* Clear and Enable Logging */
548 
549 /* DMA Transfer Control Register */
550 
551 #define DCTL_MASK 0x7f380e7f /* Reserved bits */
552 #define DCTL_L2V (1 << 31) /* PCI-to-VME transfer */
553 #define DCTL_VDW_8 (0) /* Maximum data width 8 bits */
554 #define DCTL_VDW_16 (1 << 22) /* Maximum data width 16 bits */
555 #define DCTL_VDW_32 (2 << 22) /* Maximum data width 32 bits */
556 #define DCTL_VDW_64 (3 << 22) /* Maximum data width 64 bits */
557 #define DCTL_VAS_A16 (0) /* VME address space A16 */
558 #define DCTL_VAS_A24 (1 << 16) /* VME address space A24 */
559 #define DCTL_VAS_A32 (2 << 16) /* VME address space A32 */
560 #define DCTL_VAS_USER1 (6 << 16) /* VME address space User1 */
561 #define DCTL_VAS_USER2 (7 << 16) /* VME address space User2 */
562 #define DCTL_PGM_DATA (0) /* Data AM code */
563 #define DCTL_PGM_PRGM (1 << 14) /* Program AM code */
564 #define DCTL_SUPER_USER (0) /* Non-privileged AM code */
565 #define DCTL_SUPER_SUP (1 << 12) /* Supervisor AM code */
566 #define DCTL_VCT_EN (1 << 8) /* Block mode capable */
567 #define DCTL_LD64EN (1 << 7) /* 64-bit PCI transactions */
568 
569 /* DMA Transfer Byte Count Register */
570 
571 #define DTBC_MASK 0xff000000
572 
573 /* DMA General Control/Status Register */
574 
575 #define DGCS_MASK 0x00000000 /* Reserved bits */
576 #define DGCS_GO (1 << 31) /* Start DMA */
577 #define DGCS_STOP_REQ (1 << 30) /* Stop Request */
578 #define DGCS_HALT_REQ (1 << 29) /* Halt Request */
579 #define DGCS_CHAIN (1 << 27) /* DMA chaining */
580 #define DGCS_VON_DONE (0) /* Transfer count until done*/
581 #define DGCS_VON_256 (1 << 20) /* Transfer count 256 bytes */
582 #define DGCS_VON_512 (2 << 20) /* Transfer count 512 bytes */
583 #define DGCS_VON_1024 (3 << 20) /* Transfer count 1024 bytes */
584 #define DGCS_VON_2048 (4 << 20) /* Transfer count 2048 bytes */
585 #define DGCS_VON_4096 (5 << 20) /* Transfer count 4096 bytes */
586 #define DGCS_VON_8192 (6 << 20) /* Transfer count 4096 bytes */
587 #define DGCS_VON_16384 (7 << 20) /* Transfer count 16384 bytes */
588 #define DGCS_VOFF_0 (0) /* Time off VME bus0 us */
589 #define DGCS_VOFF_16 (1 << 16) /* Time off VME bus16 us */
590 #define DGCS_VOFF_32 (2 << 16) /* Time off VME bus32 us */
591 #define DGCS_VOFF_64 (3 << 16) /* Time off VME bus64 us */
592 #define DGCS_VOFF_128 (4 << 16) /* Time off VME bus128 us */
593 #define DGCS_VOFF_256 (5 << 16) /* Time off VME bus256 us */
594 #define DGCS_VOFF_512 (6 << 16) /* Time off VME bus512 us */
595 #define DGCS_VOFF_1024 (7 << 16) /* Time off VME bus1024 us */
596 #define DGCS_ACT (1 << 15) /* DMA active */
597 #define DGCS_STOP (1 << 14) /* DMA stopped */
598 #define DGCS_HALT (1 << 13) /* DMA halted */
599 #define DGCS_DONE (1 << 11) /* DMA done */
600 #define DGCS_LERR (1 << 10) /* PCI bus error */
601 #define DGCS_VERR (1 << 9) /* VME bus error */
602 #define DGCS_P_ERR (1 << 8) /* Protocol error */
603 #define DGCS_INT_STOP (1 << 6) /* Interrupt stop enable */
604 #define DGCS_INT_HALT (1 << 5) /* Interrupt halt enable */
605 #define DGCS_INT_DONE (1 << 3) /* Interrupt done enable */
606 #define DGCS_INT_LERR (1 << 2) /* Interrupt LERR enable */
607 #define DGCS_INT_VERR (1 << 1) /* Interrupt VERR enable */
608 #define DGCS_INT_P_ERR (1) /* Interrupt protocol enable */
609 
610 /* DMA Linked List Update Enable Register */
611 
612 /* PCI Configuration Base Address Register */
613 
614 #define PCI_BS_SPACE (1) /* Memory or I/O power-up */
615 
616 /* PCI Interrupt Enable Register */
617 
618 #define LINT_EN_MASK 0xffff0000 /* Reserved bits */
619 #define LINT_EN_ACFAIL (1 << 15) /* Enable Interrupt ACFAIL */
620 #define LINT_EN_SYSFAIL (1 << 14) /* Enable Interrupt SYSFAIL */
621 #define LINT_EN_SW_INT (1 << 13) /* Enable Interrupt SW_INT */
622 #define LINT_EN_SW_IACK (1 << 12) /* Enable Interrupt SW_ACK */
623 #define LINT_EN_VERR (1 << 10) /* Enable Interrupt ACFAIL */
624 #define LINT_EN_LERR (1 << 9) /* Enable Interrupt ACFAIL */
625 #define LINT_EN_DMA (1 << 8) /* Enable Interrupt ACFAIL */
626 #define LINT_EN_VIRQ7 (1 << 7) /* Enable Interrupt VME IRQ7 */
627 #define LINT_EN_VIRQ6 (1 << 6) /* Enable Interrupt VME IRQ6 */
628 #define LINT_EN_VIRQ5 (1 << 5) /* Enable Interrupt VME IRQ5 */
629 #define LINT_EN_VIRQ4 (1 << 4) /* Enable Interrupt VME IRQ4 */
630 #define LINT_EN_VIRQ3 (1 << 3) /* Enable Interrupt VME IRQ3 */
631 #define LINT_EN_VIRQ2 (1 << 2) /* Enable Interrupt VME IRQ2 */
632 #define LINT_EN_VIRQ1 (1 << 1) /* Enable Interrupt VME IRQ1 */
633 #define LINT_EN_VOWN (1 << 0) /* Enable Interrupt VME OWN */
634 
635 /* PCI Interrupt Status Register */
636 
637 #define LINT_STAT_MASK 0xffff0800 /* Reserved bits */
638 #define LINT_STAT_ACFAIL (1 << 15) /* Status Interrupt ACFAIL */
639 #define LINT_STAT_SYSFAIL (1 << 14) /* Status Interrupt SYSFAIL */
640 #define LINT_STAT_SW_INT (1 << 13) /* Status Interrupt SW_INT */
641 #define LINT_STAT_SW_IACK (1 << 12) /* Status Interrupt SW_ACK */
642 #define LINT_STAT_VERR (1 << 10) /* Status Interrupt ACFAIL */
643 #define LINT_STAT_LERR (1 << 9) /* Status Interrupt ACFAIL */
644 #define LINT_STAT_DMA (1 << 8) /* Status Interrupt ACFAIL */
645 #define LINT_STAT_VIRQ7 (1 << 7) /* Status Interrupt VME IRQ7 */
646 #define LINT_STAT_VIRQ6 (1 << 6) /* Status Interrupt VME IRQ6 */
647 #define LINT_STAT_VIRQ5 (1 << 5) /* Status Interrupt VME IRQ5 */
648 #define LINT_STAT_VIRQ4 (1 << 4) /* Status Interrupt VME IRQ4 */
649 #define LINT_STAT_VIRQ3 (1 << 3) /* Status Interrupt VME IRQ3 */
650 #define LINT_STAT_VIRQ2 (1 << 2) /* Status Interrupt VME IRQ2 */
651 #define LINT_STAT_VIRQ1 (1 << 1) /* Status Interrupt VME IRQ1 */
652 #define LINT_STAT_VOWN (1 << 0) /* Status Interrupt VME OWN */
653 
654 #define LINT_STAT_CLEAR 0xf7ff /* clear all interrupts */
655 #define LINT_STAT_INT_MASK 0xd7ff /* mask received interrupts */
656 #define LINT_STAT_FAIL_MASK 0x0000c000 /* mask for sysfail,acfail */
657 
658 /* PCI Interrupt MAP Register 0 */
659 
660 #define LINT_MAP0_MASK 0x88888888
661 
662 /* PCI Interrupt MAP Register 1 */
663 
664 #define LINT_MAP1_MASK 0x8888f888
665 
666 /* VMEbus Interrupt Enable Register */
667 
668 #define VINT_EN_MASK 0xffffe800 /* Reserved bits */
669 #define VINT_EN_SW_INT (1 << 12) /* SW_INT interrupt generate */
670 #define VINT_EN_VERR (1 << 10) /* VERR interrupt generate */
671 #define VINT_EN_LERR (1 << 9) /* LERR enable */
672 #define VINT_EN_DMA (1 << 8) /* DMA enable */
673 #define VINT_EN_LINT7 (1 << 7) /* LINT7 enable */
674 #define VINT_EN_LINT6 (1 << 6) /* LINT6 enable */
675 #define VINT_EN_LINT5 (1 << 5) /* LINT5 enable */
676 #define VINT_EN_LINT4 (1 << 4) /* LINT4 enable */
677 #define VINT_EN_LINT3 (1 << 3) /* LINT3 enable */
678 #define VINT_EN_LINT2 (1 << 2) /* LINT2 enable */
679 #define VINT_EN_LINT1 (1 << 1) /* LINT1 enable */
680 #define VINT_EN_LINT0 (1) /* LINT0 enable */
681 
682 /* VMEbus Interrupt Status Register */
683 
684 #define VINT_STAT_MASK 0xffffe800 /* Reserved bits */
685 #define VINT_STAT_SW_INT (1 << 12) /* SW_INT interrupt active */
686 #define VINT_STAT_VERR (1 << 10) /* VERR interrupt active */
687 #define VINT_STAT_LERR (1 << 9) /* LERR interrupt active */
688 #define VINT_STAT_DMA (1 << 8) /* DMA interrupt active */
689 #define VINT_STAT_LINT7 (1 << 7) /* LINT7 interrupt active */
690 #define VINT_STAT_LINT6 (1 << 6) /* LINT6 interrupt active */
691 #define VINT_STAT_LINT5 (1 << 5) /* LINT5 interrupt active */
692 #define VINT_STAT_LINT4 (1 << 4) /* LINT4 interrupt active */
693 #define VINT_STAT_LINT3 (1 << 3) /* LINT3 interrupt active */
694 #define VINT_STAT_LINT2 (1 << 2) /* LINT2 interrupt active */
695 #define VINT_STAT_LINT1 (1 << 1) /* LINT1 interrupt active */
696 #define VINT_STAT_LINT0 (1) /* LINT0 interrupt active */
697 
698 #define VINT_STAT_CLEAR 0x17ff /* clear outgoing VME intrs. */
699 
700 /* VMEbus Interrupt Map Register 0 */
701 
702 #define VINT_MAP0_MASK 0x88888888
703 #define VINT_MAP0_MAPPING 0x76543210
704 
705 /* VMEbus Interrupt Map Register 1 */
706 
707 #define VINT_MAP1_MASK 0xfffefeee
708 #define VINT_MAP1_DMA_MASK 0x07
709 #define VINT_MAP1_DMA_LVL_1 0x01
710 #define VINT_MAP1_DMA_LVL_2 0x02
711 #define VINT_MAP1_DMA_LVL_3 0x03
712 #define VINT_MAP1_DMA_LVL_4 0x04
713 #define VINT_MAP1_DMA_LVL_5 0x05
714 #define VINT_MAP1_DMA_LVL_6 0x06
715 #define VINT_MAP1_DMA_LVL_7 0x07
716 
717 /* VMEbus Interrupt Status/ID Out Register */
718 
719 #define STATID_MASK 0x1ffffff
720 
721 /* VMEbus IRQ1 Status/ID Register */
722 
723 #define V1_STATID_ERR (1 << 8) /* Bus Error during IACK */
724 
725 /* VMEbus IRQ2 Status/ID Register */
726 
727 #define V2_STATID_ERR (1 << 8) /* Bus Error during IACK */
728 
729 /* VMEbus IRQ3 Status/ID Register */
730 
731 #define V3_STATID_ERR (1 << 8) /* Bus Error during IACK */
732 
733 /* VMEbus IRQ4 Status/ID Register */
734 
735 #define V4_STATID_ERR (1 << 8) /* Bus Error during IACK */
736 
737 /* VMEbus IRQ5 Status/ID Register */
738 
739 #define V5_STATID_ERR (1 << 8) /* Bus Error during IACK */
740 
741 /* VMEbus IRQ6 Status/ID Register */
742 
743 #define V6_STATID_ERR (1 << 8) /* Bus Error during IACK */
744 
745 /* VMEbus IRQ7 Status/ID Register */
746 
747 #define V7_STATID_ERR (1 << 8) /* Bus Error during IACK */
748 
749 /* VMEbus Master Control Register */
750 
751 #define MAST_CTL_MASK 0x0003ef00 /* Reserved bits */
752 #define MAST_CTL_RTRY_FOREVER (0 << 28) /* Max Retries before PCI err*/
753 #define MAST_CTL_PWON_128 (0 << 24) /* Posted Write VME Xfer Cnt */
754 #define MAST_CTL_PWON_256 (1 << 24) /* Posted Write VME Xfer Cnt */
755 #define MAST_CTL_PWON_512 (2 << 24) /* Posted Write VME Xfer Cnt */
756 #define MAST_CTL_PWON_1024 (3 << 24) /* Posted Write VME Xfer Cnt */
757 #define MAST_CTL_PWON_2048 (4 << 24) /* Posted Write VME Xfer Cnt */
758 #define MAST_CTL_PWON_4096 (5 << 24) /* Posted Write VME Xfer Cnt */
759 #define MAST_CTL_VRL0 (0 << 22) /* VMEbus Request Level */
760 #define MAST_CTL_VRL1 (1 << 22) /* VMEbus Request Level */
761 #define MAST_CTL_VRL2 (2 << 22) /* VMEbus Request Level */
762 #define MAST_CTL_VRL3 (3 << 22) /* VMEbus Request Level */
763 #define MAST_CTL_VRM_FAIR (1 << 21) /* FAIR Request Mode */
764 #define MAST_CTL_VRM_DEMAND (0 << 21) /* Demand Request Mode */
765 #define MAST_CTL_VREL_RWD (0 << 20) /* Release When Done */
766 #define MAST_CTL_VREL_ROR (1 << 20) /* Release on Request */
767 #define MAST_CTL_VOWN (1 << 19) /* Acquire and Hold VMEbus */
768 #define MAST_CTL_VOWN_ACK (1 << 18) /* VMEbus bus held */
769 #define MAST_CTL_PABS_32 (0 << 12) /* 32 Byte PCI Aligned Burst */
770 #define MAST_CTL_PABS_64 (1 << 12) /* 64 Byte PCI Aligned Burst */
771 #define MAST_CTL_PABS_128 (2 << 12) /* 128 Byte PCI Burst - Universe II */
772 
773 /* Miscellaneous Control Register */
774 
775 #define MISC_CTL_MASK 0x0820ffff /* Reserved bits */
776 #define MISC_CTL_VBTO_DISABLE (0 << 28) /* Forever VMEbus Timeout */
777 #define MISC_CTL_VBTO_16USEC (1 << 28) /* 16 Usec VMEbus Timeout */
778 #define MISC_CTL_VBTO_32USEC (2 << 28) /* 32 Usec VMEbus Timeout */
779 #define MISC_CTL_VBTO_64USEC (3 << 28) /* 64 Usec VMEbus Timeout */
780 #define MISC_CTL_VBTO_128USEC (4 << 28) /* 128 Usec VMEbus Timeout */
781 #define MISC_CTL_VBTO_256USEC (5 << 28) /* 256 Usec VMEbus Timeout */
782 #define MISC_CTL_VBTO_512USEC (6 << 28) /* 512 Usec VMEbus Timeout */
783 #define MISC_CTL_VBTO_1024USEC (7 << 28) /* 1024 Usec VMEbus Timeout */
784 #define MISC_CTL_VARB_PRIORITY (1 << 26) /* Priority Arbitration Mode */
785 #define MISC_CTL_VARB_RROBIN (0 << 26) /* Round Robin Arbitration */
786 #define MISC_CTL_VARBTO_DISABLE (0 << 24) /* Round Robin Arbitration */
787 #define MISC_CTL_VARBTO_16USEC (1 << 24) /* Round Robin Arbitration */
788 #define MISC_CTL_VARBTO_256USEC (2 << 24) /* Round Robin Arbitration */
789 #define MISC_CTL_SW_LRST (1 << 23) /* Software PCI Reset */
790 #define MISC_CTL_SW_SRST (1 << 22) /* Software VMEbus Sysreset */
791 #define MISC_CTL_BI_MODE (1 << 20) /* */
792 #define MISC_CTL_ENGBI (1 << 19) /* */
793 #define MISC_CTL_RESCIND (1 << 18) /* Rescinding DTACK Enable */
794 #define MISC_CTL_NO_RESCIND (0 << 18) /* Rescinding DTACK Disable */
795 #define MISC_CTL_SYSCON (1 << 17) /* Universe is SysController */
796 #define MISC_CTL_NOT_SYSCON (0 << 17) /* Universe not SysController */
797 #define MISC_CTL_V64AUTO (1 << 16) /* Initiate VME64 Auto ID */
798 
799 /* Miscellaneous Status Register */
800 
801 #define MISC_STAT_LCL_SIZE_32 (0 << 30) /* PCI Bus is 32 bits */
802 #define MISC_STAT_LCL_SIZE_64 (1 << 30) /* PCI Bus is 64 bits */
803 #define MISC_STAT_DY4AUTO (1 << 27) /* DY4 Auto ID Enable */
804 #define MISC_STAT_MYBBSY_NEGATED (1 << 21) /* Universe Bus Busy Negated */
805 #define MISC_STAT_DY4DONE (1 << 19) /* DY4 Auto ID is Done */
806 #define MISC_STAT_TXFE (1 << 18) /* Transmit FIFO Empty */
807 #define MISC_STAT_RXFE (1 << 17) /* Receive FIFO Empty */
808 
809 /* VMEbus Slave Image 0 Control */
810 
811 #define VSI0_CTL_MASK 0x1f08ff3c /* Reserved Bits */
812 #define VSI0_CTL_EN (1 << 31) /* Image Enable */
813 #define VSI0_CTL_PWEN (1 << 30) /* Posted Write Enable */
814 #define VSI0_CTL_PREN (1 << 29) /* Prefetch Read Enable */
815 #define VSI0_CTL_AM_DATA (1 << 22) /* Respond to Data AM Code */
816 #define VSI0_CTL_AM_PGM (2 << 22) /* Respond to Prog AM Code */
817 #define VSI0_CTL_AM_SUPER (2 << 20) /* Respond to Superv AM Code */
818 #define VSI0_CTL_AM_USER (1 << 20) /* Respond to Non-Priv AM Code*/
819 #define VSI0_CTL_VAS_A16 (0 << 16) /* Respond to VME A16 */
820 #define VSI0_CTL_VAS_A24 (1 << 16) /* Respond to VME A24 */
821 #define VSI0_CTL_VAS_A32 (2 << 16) /* Respond to VME A32 */
822 #define VSI0_CTL_VAS_USER1 (6 << 16) /* Respond to VME Space User 1*/
823 #define VSI0_CTL_VAS_USER2 (7 << 16) /* Respond to VME Space User 2*/
824 #define VSI0_CTL_LD64EN (1 << 7) /* Enable 64-bit PCI bus Xfer */
825 #define VSI0_CTL_LLRMW (1 << 6) /* Enable PCI lock of VME RMW */
826 #define VSI0_CTL_LAS_MEM (0 << 0) /* PCIbus Memory Space */
827 #define VSI0_CTL_LAS_IO (1 << 0) /* PCIbus I/O Space */
828 #define VSI0_CTL_LAS_CFG (2 << 0) /* PCIbus Config Space */
829 
830 /* VMEbus Slave Image 0 Base Address Register */
831 
832 #define VSI0_BS_MASK 0x00000fff
833 
834 /* VMEbus Slave Image 0 Bound Address Register */
835 
836 #define VSI0_BD_MASK 0x00000fff
837 
838 /* VMEbus Slave Image 0 Translation Offset Register */
839 
840 #define VSI0_TO_MASK 0x00000fff
841 
842 /* VMEbus Slave Image 1 Control */
843 
844 #define VSI1_CTL_MASK 0x1f08ff3c /* Reserved Bits */
845 #define VSI1_CTL_EN (1 << 31) /* Image Enable */
846 #define VSI1_CTL_PWEN (1 << 30) /* Posted Write Enable */
847 #define VSI1_CTL_PREN (1 << 29) /* Prefetch Read Enable */
848 #define VSI1_CTL_AM_DATA (1 << 22) /* Respond to Data AM Code */
849 #define VSI1_CTL_AM_PGM (2 << 22) /* Respond to Prog AM Code */
850 #define VSI1_CTL_AM_SUPER (2 << 20) /* Respond to Superv AM Code */
851 #define VSI1_CTL_AM_USER (1 << 20) /* Respond to Non-Priv AM Code*/
852 #define VSI1_CTL_VAS_A16 (0 << 16) /* Respond to VME A16 */
853 #define VSI1_CTL_VAS_A24 (1 << 16) /* Respond to VME A24 */
854 #define VSI1_CTL_VAS_A32 (2 << 16) /* Respond to VME A32 */
855 #define VSI1_CTL_VAS_USER1 (6 << 16) /* Respond to VME Space User 1*/
856 #define VSI1_CTL_VAS_USER2 (7 << 16) /* Respond to VME Space User 2*/
857 #define VSI1_CTL_LD64EN (1 << 7) /* Enable 64-bit PCI bus Xfer */
858 #define VSI1_CTL_LLRMW (1 << 6) /* Enable PCI lock of VME RMW */
859 #define VSI1_CTL_LAS_MEM (0 << 0) /* PCIbus Memory Space */
860 #define VSI1_CTL_LAS_IO (1 << 0) /* PCIbus I/O Space */
861 #define VSI1_CTL_LAS_CFG (2 << 0) /* PCIbus Config Space */
862 
863 /* VMEbus Slave Image 1 Base Address Register */
864 
865 #define VSI1_BS_MASK 0x0000ffff
866 
867 /* VMEbus Slave Image 1 Bound Address Register */
868 
869 #define VSI1_BD_MASK 0x0000ffff
870 
871 /* VMEbus Slave Image 1 Translation Offset Register */
872 
873 #define VSI1_TO_MASK 0x0000ffff
874 
875 /* VMEbus Slave Image 2 Control */
876 
877 #define VSI2_CTL_MASK 0x1f08ff3c /* Reserved Bits */
878 #define VSI2_CTL_EN (1 << 31) /* Image Enable */
879 #define VSI2_CTL_PWEN (1 << 30) /* Posted Write Enable */
880 #define VSI2_CTL_PREN (1 << 29) /* Prefetch Read Enable */
881 #define VSI2_CTL_AM_DATA (1 << 22) /* Respond to Data AM Code */
882 #define VSI2_CTL_AM_PGM (2 << 22) /* Respond to Prog AM Code */
883 #define VSI2_CTL_AM_SUPER (2 << 20) /* Respond to Superv AM Code */
884 #define VSI2_CTL_AM_USER (1 << 20) /* Respond to Non-Priv AM Code*/
885 #define VSI2_CTL_VAS_A16 (0 << 16) /* Respond to VME A16 */
886 #define VSI2_CTL_VAS_A24 (1 << 16) /* Respond to VME A24 */
887 #define VSI2_CTL_VAS_A32 (2 << 16) /* Respond to VME A32 */
888 #define VSI2_CTL_VAS_USER1 (6 << 16) /* Respond to VME Space User 1*/
889 #define VSI2_CTL_VAS_USER2 (7 << 16) /* Respond to VME Space User 2*/
890 #define VSI2_CTL_LD64EN (1 << 7) /* Enable 64-bit PCI bus Xfer */
891 #define VSI2_CTL_LLRMW (1 << 6) /* Enable PCI lock of VME RMW */
892 #define VSI2_CTL_LAS_MEM (0 << 0) /* PCIbus Memory Space */
893 #define VSI2_CTL_LAS_IO (1 << 0) /* PCIbus I/O Space */
894 #define VSI2_CTL_LAS_CFG (2 << 0) /* PCIbus Config Space */
895 
896 /* VMEbus Slave Image 2 Base Address Register */
897 
898 #define VSI2_BS_MASK 0x0000ffff
899 
900 /* VMEbus Slave Image 2 Bound Address Register */
901 
902 #define VSI2_BD_MASK 0x0000ffff
903 
904 /* VMEbus Slave Image 2 Translation Offset Register */
905 
906 #define VSI2_TO_MASK 0x0000ffff
907 
908 /* VMEbus Slave Image 3 Control */
909 
910 #define VSI3_CTL_MASK 0x1f08ff3c /* Reserved Bits */
911 #define VSI3_CTL_EN (1 << 31) /* Image Enable */
912 #define VSI3_CTL_PWEN (1 << 30) /* Posted Write Enable */
913 #define VSI3_CTL_PREN (1 << 29) /* Prefetch Read Enable */
914 #define VSI3_CTL_AM_DATA (1 << 22) /* Respond to Data AM Code */
915 #define VSI3_CTL_AM_PGM (2 << 22) /* Respond to Prog AM Code */
916 #define VSI3_CTL_AM_SUPER (2 << 20) /* Respond to Superv AM Code */
917 #define VSI3_CTL_AM_USER (1 << 20) /* Respond to Non-Priv AM Code*/
918 #define VSI3_CTL_VAS_A16 (0 << 16) /* Respond to VME A16 */
919 #define VSI3_CTL_VAS_A24 (1 << 16) /* Respond to VME A24 */
920 #define VSI3_CTL_VAS_A32 (2 << 16) /* Respond to VME A32 */
921 #define VSI3_CTL_VAS_USER1 (6 << 16) /* Respond to VME Space User 1*/
922 #define VSI3_CTL_VAS_USER2 (7 << 16) /* Respond to VME Space User 2*/
923 #define VSI3_CTL_LD64EN (1 << 7) /* Enable 64-bit PCI bus Xfer */
924 #define VSI3_CTL_LLRMW (1 << 6) /* Enable PCI lock of VME RMW */
925 #define VSI3_CTL_LAS_MEM (0 << 0) /* PCIbus Memory Space */
926 #define VSI3_CTL_LAS_IO (1 << 0) /* PCIbus I/O Space */
927 #define VSI3_CTL_LAS_CFG (2 << 0) /* PCIbus Config Space */
928 
929 /* VMEbus Slave Image 3 Base Address Register */
930 
931 #define VSI3_BS_MASK 0x0000ffff
932 
933 /* VMEbus Slave Image 3 Bound Address Register */
934 
935 #define VSI3_BD_MASK 0x0000ffff
936 
937 /* VMEbus Slave Image 3 Translation Offset Register */
938 
939 #define VSI3_TO_MASK 0x0000ffff
940 
941 /* VMEbus Register Access Image Control Register */
942 
943 #define VRAI_CTL_EN (1 << 31) /* Image Enable */
944 #define VRAI_CTL_AM_DATA (1 << 22) /* Respond to Data AM Code */
945 #define VRAI_CTL_AM_PGM (2 << 22) /* Respond to Prog AM Code */
946 #define VRAI_CTL_AM_SUPER (2 << 20) /* Respond to Superv AM Code */
947 #define VRAI_CTL_AM_USER (1 << 20) /* Respond to Non-Priv AM Code*/
948 #define VRAI_CTL_VAS_A16 (0 << 16) /* Respond to VME A16 */
949 #define VRAI_CTL_VAS_A24 (1 << 16) /* Respond to VME A24 */
950 #define VRAI_CTL_VAS_A32 (2 << 16) /* Respond to VME A32 */
951 #define VRAI_CTL_VAS_USER1 (6 << 16) /* Respond to VME Space User 1*/
952 #define VRAI_CTL_VAS_USER2 (7 << 16) /* Respond to VME Space User 2*/
953 
954 /* @prb */
955 
956 /* VMEbus CSR Control Register */
957 
958 #define VCSR_CTL_EN (1 << 31) /* Image Enable */
959 #define VCSR_CTL_LAS_MEM (0 << 0) /* PCIbus Memory Space */
960 #define VCSR_CTL_LAS_IO (1 << 0) /* PCIbus I/O Space */
961 #define VCSR_CTL_LAS_CFG (2 << 0) /* PCIbus Config Space */
962 
963 /* VMEbus AM Code Error Log */
964 
965 #define V_AMERR_MASK 0x07ffffff /* Reserved bits */
966 #define V_AMERR_IACK (1 << 25) /* */
967 #define V_AMERR_M_ERR (1 << 24) /* */
968 #define V_AMERR_V_STAT (1 << 23) /* */
969 
970 /* VMEbus CSR Bit Clear Register */
971 
972 #define VCSR_CLR_MASK 0x1fffffff /* Reserved bits */
973 #define VCSR_CLR_RESET (1 << 31) /* Negate PRST */
974 #define VCSR_CLR_SYSFAIL (1 << 30) /* Negate SysFail */
975 #define VCSR_CLR_FAIL (1 << 29) /* Board has Failed */
976 
977 /* VMEbus CSR Bit Set Register */
978 
979 #define VCSR_SET_RESET (1 << 31) /* Assert PRST */
980 #define VCSR_SET_SYSFAIL (1 << 30) /* Assert SysFail */
981 #define VCSR_SET_FAIL (1 << 29) /* Board has Failed */
982 
983 /* VMEbus CSR Bit Clear Register */
984 
985 #define VCSR_BS_MASK 0x3ffffff /* Reserved bits */
986 
987 #endif /* INCuniverseh */
UNIVERSE_CNFG_HDR
Definition: universe.h:55
UNIVERSE_REG_TYPE
Definition: universe.h:48
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