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DSM check
The purpose of the analysis is to compare various DSM inputs to the corresponding values constructed from Qtdata according to my best understanding of Eleanor's trigger document.
For the following plots, I am comparing L0dsm inputs to the Qtdata bit by bit. I take the Qtdata for the trigger crossing, and scan through available pre and post for the dsm data. The crossing with the highest number of matching bits is selected. The selection of crossing can change from event to event, and can depend on which Qt32 the data is coming from.
run10098046
Bit-wise comparison between Qtdata and L0dsm input. 0 means perfect match. 1.0 means perfect mismatch. -0.1 means no event.
High Tower comparison per Qt crate
High Tower Address comparison per Qt crate
Bit-wise comparison between Qtdata and L1dsm input. This is not L0dsm emulation. We create clusters strait from Qtdata according to Eleanor's document, and compare attiributes like adc sum and HT address to those of the L1 DSM input. At this point I am only looking at the 15 bits for the cluster sum and HT address. 0 means perfect match. 1.0 means perfect mismatch. -0.1 means no event.
The following plots use Qtdata clusters made out of qt8sums that were truncated to emulate the data packaging from Qt to L0dsm. The low 5 bits of qt8sums are suppressed, and then anything greater than 31 gets set to 31. Also, changes were made to the small cell clustering according to the updated information from Eleanor's email. Board H probably needs to be changed as well, but this has not been implemented yet.
Cluster Sum comparison per L0 DSM board. The events in L0!=3,4 where L0sum>0 and qtsum=0 seems to come from cells that should be ignored.
For comparison, if I don't truncate the qt8 sums, then I get the following correlation.
Distributions of the un-truncated qt cluster sums(black) and the L1 cluster sums(red), per module.
Extended HT address for clusters, per L0 DSM board. The vertical line segments come from the same events described earlier, where qtsum is zero and qt8 channel is (consequently) a multiple of 32, while L0 thinks that there is a valid HT and some cluster sum.
run10104023
Bit-wise comparison between Qtdata and L0dsm input. 0 means perfect match. 1.0 means perfect mismatch. -0.1 means no event.
High Tower comparison per Qt crate
High Tower Address comparison per Qt crate
Bit-wise comparison between Qtdata and L1dsm input. Again, only for the first 15 bits for cluster sum and address.
Cluster Sum comparison per L0 DSM board.
Distributions of the un-truncated qt cluster sums(black) and the L1 cluster sums(red), per module.
Extended HT address for clusters, per L0 DSM board.
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