4-tile hole in <ADC> and <TAC> QA plots
Updated on Tue, 2019-12-17 16:10. Originally created by adams92 on 2019-12-17 16:09.
In spring 2018, we were seeing occasional runs in which a group of four tiles would have low <ADC> and <TAC>.
Figure 1: QA plot for run 19126015 showing a four-tile hole in
Figure 2: QA plot for run 19126015 showing a four-tile hole in
We found that re-starting a run fixed the issue for a while, but this was obviously not a long-term solution. Steve replace the guilty daughter card for EQ3,0x1C, DC2, which fixed the issue completely. See the full thread here ("Replace EQ1 0x1C DC3" by Steve Valentino, 2018, May 04)
Figure 1: QA plot for run 19126015 showing a four-tile hole in Figure 2: QA plot for run 19126015 showing a four-tile hole in We found that re-starting a run fixed the issue for a while, but this was obviously not a long-term solution. Steve replace the guilty daughter card for EQ3,0x1C, DC2, which fixed the issue completely. See the full thread here ("Replace EQ1 0x1C DC3" by Steve Valentino, 2018, May 04)
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