The point behind a timing scan is to systematically shift the time of the ADC gate, and measure how the MIP peak responds.  When we are optimally inside the gate, the MIP peak will be largest (i.e. at highest ADC value).  When we start to cut off on one side or the other, it will fall, as we only partially integrate.  Therefore, we are looking for a "plateau" in the MIP position as a function of gate delay.

An example of a study from the 2017 run may be found here: drupal.star.bnl.gov/STAR/system/files/GateScan.pdf

We are just now getting some beam to do a similar study with our (gulp!) 744 tiles in the 2018 run.  This page reports the first attempt.

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A scan over a small range in gate delay:

Here you find a 841-page pdf file showing limited Landau fits to the ADC spectra of all 744 EPD tiles, for five gate delays.  The data were taken in the wee hours of 13 March.  The relative timing delays span [-5,+15].  (Details on first page of the pdf file)

About 150k triggers were taken with stable beam, and SiPM bia

While the fits (seen on pages 2-745) are not perfect (and it's hard to get 4000 fits perfect), it is obvious that this range of gate delays does not span the plateau.  The "strongest" MIP peak is found for timing delay "-5"



The last 30 pages are probably the most relevant.  They show the MPV (peak position) versus delay time for each channel on a given QT board.  One QT board = one page.

Here is an example, for the board in Slot 7 of Crate1:

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A scan over a wide range in gate delay:

Here you find another 841-page pdf file similar to the one described above.  This one samples a much broader range of timing delay.  Incidentally, it also has a higher bias voltage (58 V), so cannot be put onto the same plots as the 56-V data.

Here is the ADC distribution for Delay=-40,-20,0,20,40


Here is MPV versus timing delay for the same board as above:



This is consistent with the previous analysis, that more negative time delay is "better."

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