Sheet 1, MAIN

-          - This is intended for the gigabit transceiver stuff and I/O to the RDO

-          - I am using a low jitter clock OSC, Silicon labs: https://www.silabs.com/Support%20Documents/TechnicalDocs/Si590-591.pdf

-          - I need to look into if powering the gigabit transceiver is O.K. from the VCC_INT. Although both VCCINT and the gigabit power are 1.2VDC, we may need a special LDO…TBD

Sheet 2, FPGA Config.

-          Standard Xilinx platform flash configuration in JTAG chain

-          "-2 card" will populate the PROM for stand-alone operation

-          "-1 card" does not have PROM loaded
  jumper (0 ohm res) is installed for TDO line

-          I have a 4MEG PROM...However, we need to decide if we need more space considering the gigabit and USB logic?
 

Sheet 3, CCA POWER

-          I have 2x 1watt resistors on the card to simulate the load from the SAMPA ASIC

I figured that 1.2 Watts should be plenty?

-          I based the power requirements for worst case, fully loaded SPARTAN 6 design.

1.5 ADC low noise, LDO’s, SOT 223, so they should fit nicely on the board.

12/24/13

I propse we have 5VDC as digital power. I need something atleast 1 volt higher to power the 3.3VDC LDO's.
The current FEE uses 4v, thats fine also.

3.3 VDC --> Analog power (SAMPA ASIC)
BTW: I assume the SAMPA will have 1 supply (maybe 2 supplies, VCC and VDD?) but 2x grounds, DIG_GND and AGND
most likely it will follw other ADC designs and the grounds get tied together with a short trace length.


Ripple Voltage... Limit 10mv p-p for MGT power as per Xilinx spec.
 

Sheet 4, 3.3 volt logic

-          8 Bit test header for debugging 2mm, but may change to .1 pitch because it’s easier to connect the logic probe to

-          1 wire temperature with 48 bit ID

-          Local OSC, low jitter 40MHZ

-          Reset pushbutton or RDO driven
 

Sheet 5, 2.5 volt logic

-          Right now jut the iFEE address and i2C data to SAMPA