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I captured the period jitter from the TCD card with various time delays.

Test Set-up:

-TCD running from RCC clock (data run).

-clock out from front panel of TCD card --> oscilloscope capture

-Histogram: StdDev (RMS), Peak-Peak jitter

-trigger on rising edged --> look at next rising edge for jitter--> see comments tab.

The jitter varies as the delay changes --> note: from 19ns to 18ns

15ns seems the worst case with the tested delays:

Here I also examined the third rising edge after trigger and the jitter appears a bit worse:

115   |139ps            |1.3ns                  |2nd rising edge after trigger

115   |219ps            |1.6ns                  |3d rising edge after trigger

NOTE: Probably need to look at more subsequent edges ?

-------------------------------------------------------------------------------------------------

 If the card is not the issue and we need more testing....

 What I would like to do is:

 Examine the jitter right at one of the crates and see how the TCD clock in relates to the trigger data.

 I am thinking that maybe a more controlled test:

 -Mask out all but one channel in the crate
-Set the filter in the slow controls to least sensitive (higher order bits)
-inject a test pulse and trigger from the TCD card

 Delay

(ns)  |RMS        |Peak - Peak            |comment

114   |137ps            |1.17ns           |2nd rising edge after trigger

115   |139ps            |1.3ns             |2nd rising edge after trigger

115   |219ps            |1.6ns             |3d rising edge after trigger

116   |91ps       |724ps                  |2nd rising edge after trigger

117   |115.5ps    |1.4ns                  |2nd rising edge after trigger

118   |121ps            |1.22ns           |2nd rising edge after trigger

119   |91.9ps     |876ps                  |2nd rising edge after trigger

Tim Camarda

STAR Physics Dept.

Brookhaven National Lab.

Bldg. 901W

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