Updated pinout request as per Tonkos email from Feb 18 2014

RHIC_CLK_P --> G9
RHIC_CLK_N --> G11

- Included I2C EEPROM for testing 1MHZ comm to FPGA host

- Added breakout test pins for SAMPA signals

- GTP updated to 135MHZ part no.

-Local FPGA CLK --> 50 MHZ

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NOTE on SAMPA loopback:

Xilinx limits the Spartan 6 as follows for LVDS:

BANKS 0, 2 --> IN/ OUT pins

BANKS 1,3 --> INPUT ONLY

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Added 2.5VDC power rail for LVDS25