iFEE schematic update 01_07_2014

IFEE prototype CCA design notes:

https://docs.google.com/file/d/0B646cEWOsHZKaVdxczBjVDZvazg/edit?pli=1

  • Changed flash PROM to 16MB, TSSOP 48 pin

  • Changed local JTAG connector to match Xilinx platform flash USB adapter (2mm header)

  • Corrections as per Tonko’s email 12/30/2013

  • Misc. additions corrections

  • Added diff. pair loopback test option

 

Power rail notes:

 

  • VCCO_3_3 will power both 3.3VDC I/O banks

  • Included VCC_MGT,  LDO to power gigabit transceivers

  • BANK 0,1: SAMPA Data (VCCO for SAMAP is TBD)

  • BANK 2,3: 3_3 VDC I/O

 

NOTE: Some requirements call out for ferrite beads on the MGT power rails (not sure right now if this was applicable to SPARTAN 6). However, this will not work near the magnet. Will have to rely on good decoupling practices and keeping trace inductance to a minimum.

 

FEE to RDO connections:

 

-We will use the 36 pin SATA iPASS cable type 1 configuration, mating to molex PN: 75783-0140

-The pin-out and signal designation is agreed upon for both the RDO and FEE

-All signals (except the gigabit data) will be buffered at the RDO end

NOTE: We are considering buffering the GTP data between Spartan 6 and Atrix 7

Also, we may need to AC couple transmission lines... TBD

If Active Buffering is permitted then suggest this device from Micrel: http://www.micrel.com/_PDF/HBW/sy54016ar.pdf
 

 

Gigabit data logic family:

 

  • According to Xilinx, it is recommended to set the logic for the gigabit data to CML.

  • Better control of pre-emphasis “over-shoot”.

  • Trace impedance (strip-line) for gigabit data is to be controlled on the PCB layers to match 100Ω

 
 

PCB Layout Considerations:

 

  • Some of the routing/ layout rules have been defined 

  • Some high speed rules used are generic/ good practice

  • Gigabit traces (aggressor pairs) are to be at least 5x trace width distance from other signals.

  • Run gigabit data traces as “stripline”

  • No 90’ bends for high speed signals including SAMPA data to FPGA (chamfer all bends)

 

Ground Noise/ loops

 

  • Be mindful of ground loops and ground shifting effects on transmission from RDO to FEE cards

  • Probably not an issue since both the FEE and RDO will be grounded to magnet (common tie point)

 

USB power option:

- It appears we may be able to power a FEE or group of FEE's from a USB powerd extender HUB.
- Although, this may require us to build a custom HUB with COTS parts as the available HUBS may not be adequate since they derate the power as per device attached.