- FPGA pinout changes for PCB optimization

- Refer to iFEE_FPGA_pinout_changes_03_12_14.htm

- Refer to U1_netlist_03_12_14.txt for FPGA netlist

- PCB routing ~80% completed. I believe the layout is favorably optimized...may need to move a few pins.

- PCB details: 8 Layers, Tg170 FR4 (high temp for ROHS BGA), Dimensions 170mm x 60.4 (width of edge card).

- So, this card is slightly shorter and narrower than the present FEE stick

- Top Layer --> signal, GTP Lane

- LAYER 2 --> DIG_GND

- LAYER 3 --> LS SIGNALS

- LAYER 4 --> POWER

- LAYER 5 --> POWER

- LAYER 6 HS Signals --> may use for stripline run for HS Diff. SAMPA data

- LAYER 7 --> ANLG / DIG GRND

- Bottom Layer --> signal layer, HS Diff.

The signal layers are designed for controlled impedance for the HS differential signals and GTP lane

- GTP (top layer) should be controlled for ~100 ohms as per the Xilinx spec stating 100 ohms differential termination (each side 50 ohms to GND).

- For this first spin we will LVDS_2_5 for the SAMPA data loop back testing. The SAMPA diff. data should also be controlled for ~100 ohms ( maybe 120, need to verify). This may change for the actual ASIC.

- General good practice rules applied for trace optimization and minimizing inductance

- Right now, I don't believe that any component requires a copper cut-out for the ground plane.

- This is usually done for HS analog circuits, for noise immunity and to prevent oscillations. So, we should have a continues ground plane (at least for the digital ground).

I believe heat sinking efficiency is improved by using copper pour areas to directly attach to the heat/ sink bracket. The bracket final shape / size is dependent on the strong back re-design.

I include 2x mounting holes and designed the PCB placement and copper pour areas (as per conversation with Bob) to accommodate a proposed heat sink...but this is still TBD

Based on power and thermal estimates, the card should have adequate heat sinking for standalone operation when not attached to the TPC.

However, since we have no component packaging information, thermal transfer data is only a best guest right now regarding the SAMAP ASIC's. (The power and heat generation for the ASIC's are being simulated with a resistive load, for ~ 1 watt! / ASIC).

I do not know the exact temperature, but according the Howard Wieman, the area where the FEE card makes connection to the TPC...we need to prevent an over build up of heat, since it may affect the gas temperature. I would assume that we should keep this section between 30-32 degrees C...TBD