This is nearing the final design for TUFF control box and power distribution to FPS FEE's

- One wire opto circuit resistor values changed for 3.3v instead of 5v

    Schematic Scheets:

-->MAIN

- Power and OWB distribution from HD15 DB connectors.

- DB15 are PCB mount and can be placed either on the front or rear pannel of TUFF box

- A/D circuit addressed 0-2 to readback pos 6, neg 6 and neg 90v

-->POWER

- Power is brought in from a circular DIN connector mounted on the TUFF chasis

- then wired to a PCB mount terminal block

- input filtering/ signal conditioning and fuses as requiered (ferite chokes)

- All rails (except 1.8vdc for platform flash) have pilot lights

--FROT PANEL INDICATORS

- An LED light pipe (same as we used for ARCII) will indicate power on/off status to each group--> HV ON and LV ON

NOTE: considering using blue leds for HV, but will need to add 5v LDO for buffer

- 2 push button switches used to cycle a menu for the TFT display --> see SBC sheet

-- LDO sequence --> AUX powers first, then 1.8v for flash chip then other LDO's

-->FPGA CONFIG and POWER

-- 16meg Xilinx platform flash

-- Reset jumper (re-configure FPGA), will probably put reset switch on front panel

-- 2mm r/a header --> JTAG port accesable from FP

--> SBC embedded LINUX connectcore 9P 9215

- data and control to FPGA same as TCD card

- TFT display (PN: JDT1800) is used in SPI mode 0 slave
- SBC UART configured for SPI master, mode 0 , same as ARCII
- TFT displat will mount on TUFF FP and connect through header pins

- RJ45/ transformer Ethernet FP connector

-->ONE WIRE BUS I/O

-Optical transceiver circuit for one wire bus bridge to FEE cards

-resistor values changed for 3.3v instead of 5v