I examined the files taken by Oleg Tsai
Runs14062066 onwards
Run Timing
x66 104/0
x67 104/5
x68 105/0
x69 105/5
x70 105/8
x72 106/1
x77 106/4
x78 106/7
x79 107/0
x80 107/3
x81 107/7
x82 108/0
x83 103/5
x84 103/0
x85 106/0

I made a plot of the sum of (adc-ped)>800 for all 8 SMD crates (phi hits only...eta hits had noise problems)
I find an average delay optimum of 185.1 ns, where zero corresponds to Coarse/Fine = 104/0, implying an
optimum setting for 2013

Coarse = 104 + modulo(185.1,106.6) = 105
Fine      = (185.1-106.6)/(106.6/10) = 7.3 = 7

Coarse = 105/7