computing

B-EMC / Spin db

-00-00
Thursday, 1 January 1970
, at 00:00 (GMT), duration : 00:00
We will have an opened meeting to discussed perceived or real database issues the Spin PWG seem to be having.
Attendees were: David Relya, Alex Suaide, Mike Miller and Will Jacobs.
TimeTalkPresenter
14:00Email exchange, db sanity check ( 00:10 ) 0 files
14:20How to set times in database and their meanings ( 00:10 ) 0 files
14:30MySQL level db checks ( 00:10 ) 1 file

Field Issues

Under:
This is meant to be a central location for finding reconstruction-related items which have some field dependences.

AuAu200 (2005)

GridLeak Simulations

Under:
Nikolai Smirnov & Alexei Lebedev:
Data for STAR TPC supersector.   05.05.2005  07.11.2005
Jon Wirth, who build all sectors provide these data.

Gated Grid Wires: 0.075mm Be Cu, Au plated, spacing 1mm
Outer Sector 689 wires, Inner Sector 681 wires. Total 1370 wires per sector

Cathode Grid Wires: 0.075mm Be Cu, Au plated, spacing 1mm
Outer Sector 689 wires, Inner Sector 681 wires. Total 1370 wires per sector

Anode Grid Wires:0.020mm W, Au plated, spacing 4mm
Outer Sector 170 wires, Inner Sector 168 wires. Total 338 wires per sector
Last Anode Wires: 0.125mm Be Cu, Au plated
Outer Sector 2 wires, Inner Sector 2 wires. Total 4 wires per sector

We are most interested in the gap between Inner and Outer sector, where ion leak is important for space charge. On fig. 1 wires set is shown. The distance between inner and outer gating grid is 16.00 mm. When Grid Gate is closed, the border wires in Inner and Outer sectors have -40V, each next wire have -190V and after this pattern preserved in whole sector - see fig. 2. When gating grid is open, each wire in gating grid have the same potential -115V. Above grid plane we have a drift volume with E~134V/cm to move electrons from tracks to sectors and repulse ions to central membrane. Cathode plane has zero voltage, while anode wires for outer sector holds +1390V and for inner sector +1170V.


Fig. 1. Wire structure between Inner and Outer sector.


Fig.2 Voltages applied to Gating Grid with grid closed.

Another configurations of voltages on gating grid wires are presented on fig.3. All these voltages are possible by changing wire connections in gating grid driver. Garfield simulations should be performed for all to find a minimum ion leak.


Fig.3 Different voltages on closed gating grid (top: inverted, bottom: mixed).

This is a key for Nikolai's files: there are 4 sets of files in each set there is simulation for Gating Grid voltages on last wires. Additionally he artificially put a ground shield on the level of cathode plane and simulated collection for last-thick anode wire and also ground shield and last thin anode wire.

Setups: Standard Inverted Mixed Ground Strip Ground Strip
and Wire
Equipotentials PS

PS

PS

PS

PS

Electron paths PS

PS

PS

PS

PS

Ion paths
(inner sector)
PS

PS

PS

PS

PS

Ion paths
(outer sector)
PS

PS

PS

PS

PS

Software and Computing phone meeting

-00-00
Thursday, 1 January 1970
, at 00:00 (GMT), duration : 00:00
TimeTalkPresenter
12:00PWG issues overview, past issues ( 00:10 ) 0 filesJames Dunlop (BNL)
12:10Cu+Cu: Investigation of pile-up ( 00:20 ) 0 filesDan Magestro & al. (OSU)
12:30SVT alignement recent progress ( 00:10 ) 0 filesSpiros Margetis (KSU)
12:40Event by Event STI comparison (followup) ( 00:10 ) 0 filesYuri Fisyak (BNL)
12:50AOB ( 00:10 ) 0 filesAll

Software and Computing phone meeting

-00-00
Thursday, 1 January 1970
, at 00:00 (GMT), duration : 00:00
TimeTalkPresenter
12:00QA on the new productions of CuCu @ 200 GeV ( 00:10 ) 0 filesChristine Nattrass (Yale)
12:10The Effects of the Inclusion of SVT Hits in the Reconstruction of K0Shorts ( 00:10 ) 0 filesAnthony Timmins (BHAM)
12:20B-EMC calibration status and revised agenda ( 00:10 ) 0 filesAdam Kocoloski (MIT)
12:30E-EMC status and timeline for readiness for Y6 p+p ( 00:10 ) 0 filesJan Balewski (TBC) (IUCF)
12:40Library readiness for SVT+SSD+Vertex ( 00:10 ) 0 filesLidia Didenko (BNL)
12:50XML Geometry demonstration ( 00:10 ) 0 filesMaxim Potekhin (BNL)

SVT/SSD software and alignement effort - SVT(SSD) Review Coordination meeting

-00-00
Thursday, 1 January 1970
, at 00:00 (GMT), duration : 00:00
TimeTalkPresenter
12:20Heavy Flavor and Spin Physics Working Group ( 00:10 ) 1 filenone
12:30SVT review thoughts ( 00:10 ) 3 filesSpiros Margetis (KSU)

Software and Computing phone meeting

-00-00
Thursday, 1 January 1970
, at 00:00 (GMT), duration : 00:00
TimeTalkPresenter
12:00Embedding update, status and readiness ( 00:10 ) 1 fileAndrew Rose (LBNL)
12:10Spin PWGC official request ( 00:10 ) 0 filesMe (BNL)
12:20FTPC calibration update ( 00:10 ) 0 filesTerrence Tarnowsky (Purdue)
12:30General calibration update and readiness ( 00:10 ) 0 filesGene Van Buren (BNL)
12:40Ongoing production status and timelines ( 00:10 ) 0 filesLidia Didenko (BNL)
13:00Library readiness, ROOT5, etc ... ( 00:10 ) 0 filesAll

Software and Computing phone meeting

-00-00
Thursday, 1 January 1970
, at 00:00 (GMT), duration : 00:00
TimeTalkPresenter
12:00TPC BeamLine constraint update ( 00:10 ) 0 filesGene Van Buren (BNL)
12:10Embedding news for QM & summary ( 00:10 ) 1 fileOlga Barannikova / Andrew Rose
12:20ROOT 5 issues, plan forward, patch? ( 00:10 ) 0 filesTBC
12:30AOB ( 00:10 ) 0 filesAll (All)

Software and Computing phone meeting

-00-00
Thursday, 1 January 1970
, at 00:00 (GMT), duration : 00:00
TimeTalkPresenter
12:00Vertex finding with Minuit ( 00:15 ) 0 filesMarco van Leeuwen (LBNL)
12:15Sti status, summary of pulls ( 00:15 ) 1 fileYuri Fisyak (BNL)
12:30SVT progress and review preparation ( 00:15 ) 0 filesSpiros Margetis (KSU)
12:45Enriched simulation sample (SVT review prep) ( 00:10 ) 1 fileMaxim Potekhin (BNL)
12:50AOB ( 00:10 ) 0 filesAll

Software and Computing phone meeting

-00-00
Thursday, 1 January 1970
, at 00:00 (GMT), duration : 00:00
TimeTalkPresenter
12:00Data production overview ( 00:10 ) 0 filesLidia Didenko (BNL)
12:10Run VII QA preparation ( 00:10 ) 0 filesLanny Ray (UTA)
12:20Run 6, pp 62 GeV calibration ( 00:10 ) 0 filesGene Van Buren (BNL)
12:40DEV/ ROOT 5 feedback ( 00:10 ) 0 filesAll (All)
12:50AOB ( 00:10 ) 0 filesAll (All)
13:10Qt work in dev, EventDisplay recent developments ( 00:10 ) 1 fileValeri Fine (BNL)

Software and Computing phone meeting

-00-00
Thursday, 1 January 1970
, at 00:00 (GMT), duration : 00:00
TimeTalkPresenter
12:00News from the front ( 00:10 ) 0 filesHal Spinka (ANL)
12:10Results from Cu+Cu vertex finding ( 00:10 ) 0 filesAnthony Timmins (BHAM)
12:20Track parameters extension & vertex errors - proposal ( 00:10 ) 0 filesYuri Fisyak (BNL)
12:30SVT review data samples, overview ( 00:10 ) 0 filesMoi (BNL)
12:40SVT/SSD review production library status (P06ic) ( 00:10 ) 0 filesLidia Didenko (BNL)
12:50Spin PWG simulation status ( 00:10 ) 0 filesMaxim Potekhin (BNL)
13:00AOB ( 00:10 ) 0 filesAll

Software and Computing phone meeting

-00-00
Thursday, 1 January 1970
, at 00:00 (GMT), duration : 00:00
TimeTalkPresenter
12:00p+p Run6 Spin PWG QA ( 00:10 ) 0 filesAdam Kocoloski (MIT)
12:10SSD software embedding simulation update ( 00:10 ) 1 fileJonathan Bouchet (Subatech)
12:20Calibration R&D and recent findings ( 00:10 ) 2 filesGene Van Buren (BNL)
12:30Error fitting in Sti ( 00:10 ) 1 fileVictor Perevoztchikov (BNL)
12:40Progress toward ROOT 5 ( 00:10 ) 0 filesValeri Fine (BNL)
12:50R&D simulation updates ( 00:10 ) 0 filesMaxim Potekhin (BNL)

Software and Computing phone meeting

-00-00
Thursday, 1 January 1970
, at 00:00 (GMT), duration : 00:00
TimeTalkPresenter
12:00R&D meetign summary from December 13th phone meeting ( 00:10 ) 0 filesJ. Lauret (BNL)
12:10R&D follow-up: Pulls in IST ( 00:10 ) 0 filesMike Miller (MIT)
12:20R&D AOB ( 00:10 ) 0 filesAll (All)
12:30BBC Signature of TPC background ( 00:10 ) 0 filesGene Van Buren (BNL)
12:40ROOT patching scheme discussion ( 00:10 ) 0 filesAll (All)
12:50AOB ( 00:10 ) 0 filesAll (All)

Software and Computing phone meeting

-00-00
Thursday, 1 January 1970
, at 00:00 (GMT), duration : 00:00
TimeTalkPresenter
12:00Embedding status ( 00:15 ) 0 filesAndrew Rose (LBNL)
12:15Production status ( 00:10 ) 0 filesLidia Didenko (BNL)
12:25imulation geometry for inner tracker R&D, convergence? ( 00:10 ) 0 filesMaxim Potekhin (BNL)
12:35Code changes for inner tracker R&D, other changes ... ( 00:10 ) 0 filesYuri Fisyak (BNL)
12:45AOB ( 00:10 ) 0 filesAll (All)

Software and Computing phone meeting

-00-00
Thursday, 1 January 1970
, at 00:00 (GMT), duration : 00:00
TimeTalkPresenter
12:00SL06d library readiness and main changes ( 00:10 ) 0 filesLidia Didenko (BNL)
12:10Overview of reconstruction changes in SL06d ( 00:10 ) 0 filesYuri Fisyak (BNL)
12:20Cu+Cu SVT/SSD review data samples QA ( 00:10 ) 0 filesChristine Nattrass (Yale)
12:45p+p production times ( 00:10 ) 0 filesJerome Lauret (BNL)
12:55AOB ( 00:05 ) 0 filesAll (All)
13:00P06 calibration view, sDCA ( 00:10 ) 0 filesGene Van Buren (BNL)

Software and Computing phone meeting

-00-00
Thursday, 1 January 1970
, at 00:00 (GMT), duration : 00:00
TimeTalkPresenter
12:00Simulation recent developments ( 00:15 ) 0 filesMaxim Potekhin (BNL)
12:15SSD embedding, progress report ( 00:15 ) 1 fileJonathan Bouchet (Subatech)
12:30Production status for QM06, status ( 00:10 ) 0 filesLidia Didenko (BNL)
12:40Xrootd status, activities and remaining problems ( 00:10 ) 1 filePavel Jakl (NPI-AS)
12:50AOB ( 00:10 ) 0 filesAll (All)

Software and Computing phone meeting

-00-00
Thursday, 1 January 1970
, at 00:00 (GMT), duration : 00:00
TimeTalkPresenter
12:00News from the front ( 00:15 ) 0 filesChuck Whitten (UCLA)
12:15Simulation for the SVT review ( 00:10 ) 0 filesMaxim Potekhin (BNL)
12:25Library stability ( 00:10 ) 0 filesLidia Didenko (BNL)
12:35AOB ( 00:10 ) 0 filesAll

Software and Computing phone meeting

-00-00
Thursday, 1 January 1970
, at 00:00 (GMT), duration : 00:00
TimeTalkPresenter
12:00News from the front ( 00:10 ) 0 filesChuck Whitten (UCLA)
12:10Cu+Cu production, timeline and samples overview ( 00:10 ) 0 filesLidia Didenko (BNL)
12:20Opened discussion ( 00:10 ) 0 filesAll
12:30TPC Twist calibration progress ( 00:10 ) 0 filesEric Hjort (LBNL)
12:40GridLeak distortion progress ( 00:10 ) 0 filesGene Van Buren (BNL)
12:50Simulation request for SPin ( 00:10 ) 0 filesMaxim Potekhin (BNL)

Software and Computing phone meeting

-00-00
Thursday, 1 January 1970
, at 00:00 (GMT), duration : 00:00
TimeTalkPresenter
12:00SVT Embedding readiness overview ( 00:15 ) 1 fileHelen Caines (Yale)
12:15SSD simulation software chain status, embeding perspectives ( 00:15 ) 1 fileJonathan Bouchet (Subatech)
12:30Strangeness PWG perspective of the includion of SVT/SSD ( 00:15 ) 0 filesChristine Nattrass (Yale)
12:45HighPt PWG perspectives ( 00:10 ) 0 filesMarco van Leeuwen (LBNL)
12:55AOB ( 00:05 ) 0 filesAll (All)

Software and Computing phone meeting

-00-00
Thursday, 1 January 1970
, at 00:00 (GMT), duration : 00:00
TimeTalkPresenter
12:00Year6 p+p (TPC) calibration status ( 00:10 ) 0 filesGene Van Buren (BNL)
12:10Cu+Cu 200 GeV possible issues ( 00:10 ) 0 filesYuri Fisyak (BNL)
12:20Simulation, new SVT review request ( 00:10 ) 0 filesMaxim Potekhin (BNL)
12:30Xrootd status and recent developments ( 00:10 ) 1 filePavel Jakl (NPI-AS)
12:50AOB ( 00:10 ) 0 filesAll (All)
13:00Database load balancer, status and next step ( 00:10 ) 1 fileMike DePhillips (BNL)