computing
B-EMC / Spin db
, at 00:00 (GMT), duration : 00:00
Attendees were: David Relya, Alex Suaide, Mike Miller and Will Jacobs.
Time | Talk | Presenter |
---|---|---|
14:00 | Email exchange, db sanity check ( 00:10 ) 0 files | |
14:20 | How to set times in database and their meanings ( 00:10 ) 0 files | |
14:30 | MySQL level db checks ( 00:10 ) 1 file |
Field Issues
Updated on Tue, 2006-01-17 20:09. Originally created by genevb on 2006-01-17 19:10. Under:
GridLeak Simulations
Updated on Thu, 2013-06-27 17:19 by testadmin. Originally created by genevb on 2006-01-13 16:33. Under:Data for STAR TPC supersector. 05.05.2005 07.11.2005 Jon Wirth, who build all sectors provide these data. Gated Grid Wires: 0.075mm Be Cu, Au plated, spacing 1mm Outer Sector 689 wires, Inner Sector 681 wires. Total 1370 wires per sector Cathode Grid Wires: 0.075mm Be Cu, Au plated, spacing 1mm Outer Sector 689 wires, Inner Sector 681 wires. Total 1370 wires per sector Anode Grid Wires:0.020mm W, Au plated, spacing 4mm Outer Sector 170 wires, Inner Sector 168 wires. Total 338 wires per sector Last Anode Wires: 0.125mm Be Cu, Au plated Outer Sector 2 wires, Inner Sector 2 wires. Total 4 wires per sector
We are most interested in the gap between Inner and Outer sector, where ion leak is important for space charge. On fig. 1 wires set is shown. The distance between inner and outer gating grid is 16.00 mm. When Grid Gate is closed, the border wires in Inner and Outer sectors have -40V, each next wire have -190V and after this pattern preserved in whole sector - see fig. 2. When gating grid is open, each wire in gating grid have the same potential -115V. Above grid plane we have a drift volume with E~134V/cm to move electrons from tracks to sectors and repulse ions to central membrane. Cathode plane has zero voltage, while anode wires for outer sector holds +1390V and for inner sector +1170V.
Fig. 1. Wire structure between Inner and Outer sector.
Fig.2 Voltages applied to Gating Grid with grid closed.
Another configurations of voltages on gating grid wires are presented on fig.3. All these voltages are possible by changing wire connections in gating grid driver. Garfield simulations should be performed for all to find a minimum ion leak.
Fig.3 Different voltages on closed gating grid (top: inverted, bottom: mixed).
This is a key for Nikolai's files: there are 4 sets of files in each set there is simulation for Gating Grid voltages on last wires. Additionally he artificially put a ground shield on the level of cathode plane and simulated collection for last-thick anode wire and also ground shield and last thin anode wire.
Setups: | Standard | Inverted | Mixed | Ground Strip | Ground Strip and Wire |
---|---|---|---|---|---|
Equipotentials | PS |
PS |
PS |
PS |
PS |
Electron paths | PS |
PS |
PS |
PS |
PS |
Ion paths (inner sector) |
PS |
PS |
PS |
PS |
PS |
Ion paths (outer sector) |
PS |
PS |
PS |
PS |
PS |
Software and Computing phone meeting
, at 00:00 (GMT), duration : 00:00
Time | Talk | Presenter |
---|---|---|
12:00 | PWG issues overview, past issues ( 00:10 ) 0 files | James Dunlop (BNL) |
12:10 | Cu+Cu: Investigation of pile-up ( 00:20 ) 0 files | Dan Magestro & al. (OSU) |
12:30 | SVT alignement recent progress ( 00:10 ) 0 files | Spiros Margetis (KSU) |
12:40 | Event by Event STI comparison (followup) ( 00:10 ) 0 files | Yuri Fisyak (BNL) |
12:50 | AOB ( 00:10 ) 0 files | All |
Software and Computing phone meeting
, at 00:00 (GMT), duration : 00:00
Time | Talk | Presenter |
---|---|---|
12:00 | QA on the new productions of CuCu @ 200 GeV ( 00:10 ) 0 files | Christine Nattrass (Yale) |
12:10 | The Effects of the Inclusion of SVT Hits in the Reconstruction of K0Shorts ( 00:10 ) 0 files | Anthony Timmins (BHAM) |
12:20 | B-EMC calibration status and revised agenda ( 00:10 ) 0 files | Adam Kocoloski (MIT) |
12:30 | E-EMC status and timeline for readiness for Y6 p+p ( 00:10 ) 0 files | Jan Balewski (TBC) (IUCF) |
12:40 | Library readiness for SVT+SSD+Vertex ( 00:10 ) 0 files | Lidia Didenko (BNL) |
12:50 | XML Geometry demonstration ( 00:10 ) 0 files | Maxim Potekhin (BNL) |
SVT/SSD software and alignement effort - SVT(SSD) Review Coordination meeting
, at 00:00 (GMT), duration : 00:00
Time | Talk | Presenter |
---|---|---|
12:20 | Heavy Flavor and Spin Physics Working Group ( 00:10 ) 1 file | none |
12:30 | SVT review thoughts ( 00:10 ) 3 files | Spiros Margetis (KSU) |
Software and Computing phone meeting
, at 00:00 (GMT), duration : 00:00
Time | Talk | Presenter |
---|---|---|
12:00 | Embedding update, status and readiness ( 00:10 ) 1 file | Andrew Rose (LBNL) |
12:10 | Spin PWGC official request ( 00:10 ) 0 files | Me (BNL) |
12:20 | FTPC calibration update ( 00:10 ) 0 files | Terrence Tarnowsky (Purdue) |
12:30 | General calibration update and readiness ( 00:10 ) 0 files | Gene Van Buren (BNL) |
12:40 | Ongoing production status and timelines ( 00:10 ) 0 files | Lidia Didenko (BNL) |
13:00 | Library readiness, ROOT5, etc ... ( 00:10 ) 0 files | All |
Software and Computing phone meeting
, at 00:00 (GMT), duration : 00:00
Time | Talk | Presenter |
---|---|---|
12:00 | TPC BeamLine constraint update ( 00:10 ) 0 files | Gene Van Buren (BNL) |
12:10 | Embedding news for QM & summary ( 00:10 ) 1 file | Olga Barannikova / Andrew Rose |
12:20 | ROOT 5 issues, plan forward, patch? ( 00:10 ) 0 files | TBC |
12:30 | AOB ( 00:10 ) 0 files | All (All) |
Software and Computing phone meeting
, at 00:00 (GMT), duration : 00:00
Time | Talk | Presenter |
---|---|---|
12:00 | Vertex finding with Minuit ( 00:15 ) 0 files | Marco van Leeuwen (LBNL) |
12:15 | Sti status, summary of pulls ( 00:15 ) 1 file | Yuri Fisyak (BNL) |
12:30 | SVT progress and review preparation ( 00:15 ) 0 files | Spiros Margetis (KSU) |
12:45 | Enriched simulation sample (SVT review prep) ( 00:10 ) 1 file | Maxim Potekhin (BNL) |
12:50 | AOB ( 00:10 ) 0 files | All |
Software and Computing phone meeting
, at 00:00 (GMT), duration : 00:00
Time | Talk | Presenter |
---|---|---|
12:00 | Data production overview ( 00:10 ) 0 files | Lidia Didenko (BNL) |
12:10 | Run VII QA preparation ( 00:10 ) 0 files | Lanny Ray (UTA) |
12:20 | Run 6, pp 62 GeV calibration ( 00:10 ) 0 files | Gene Van Buren (BNL) |
12:40 | DEV/ ROOT 5 feedback ( 00:10 ) 0 files | All (All) |
12:50 | AOB ( 00:10 ) 0 files | All (All) |
13:10 | Qt work in dev, EventDisplay recent developments ( 00:10 ) 1 file | Valeri Fine (BNL) |
Software and Computing phone meeting
, at 00:00 (GMT), duration : 00:00
Time | Talk | Presenter |
---|---|---|
12:00 | News from the front ( 00:10 ) 0 files | Hal Spinka (ANL) |
12:10 | Results from Cu+Cu vertex finding ( 00:10 ) 0 files | Anthony Timmins (BHAM) |
12:20 | Track parameters extension & vertex errors - proposal ( 00:10 ) 0 files | Yuri Fisyak (BNL) |
12:30 | SVT review data samples, overview ( 00:10 ) 0 files | Moi (BNL) |
12:40 | SVT/SSD review production library status (P06ic) ( 00:10 ) 0 files | Lidia Didenko (BNL) |
12:50 | Spin PWG simulation status ( 00:10 ) 0 files | Maxim Potekhin (BNL) |
13:00 | AOB ( 00:10 ) 0 files | All |
Software and Computing phone meeting
, at 00:00 (GMT), duration : 00:00
Time | Talk | Presenter |
---|---|---|
12:00 | p+p Run6 Spin PWG QA ( 00:10 ) 0 files | Adam Kocoloski (MIT) |
12:10 | SSD software embedding simulation update ( 00:10 ) 1 file | Jonathan Bouchet (Subatech) |
12:20 | Calibration R&D and recent findings ( 00:10 ) 2 files | Gene Van Buren (BNL) |
12:30 | Error fitting in Sti ( 00:10 ) 1 file | Victor Perevoztchikov (BNL) |
12:40 | Progress toward ROOT 5 ( 00:10 ) 0 files | Valeri Fine (BNL) |
12:50 | R&D simulation updates ( 00:10 ) 0 files | Maxim Potekhin (BNL) |
Software and Computing phone meeting
, at 00:00 (GMT), duration : 00:00
Time | Talk | Presenter |
---|---|---|
12:00 | R&D meetign summary from December 13th phone meeting ( 00:10 ) 0 files | J. Lauret (BNL) |
12:10 | R&D follow-up: Pulls in IST ( 00:10 ) 0 files | Mike Miller (MIT) |
12:20 | R&D AOB ( 00:10 ) 0 files | All (All) |
12:30 | BBC Signature of TPC background ( 00:10 ) 0 files | Gene Van Buren (BNL) |
12:40 | ROOT patching scheme discussion ( 00:10 ) 0 files | All (All) |
12:50 | AOB ( 00:10 ) 0 files | All (All) |
Software and Computing phone meeting
, at 00:00 (GMT), duration : 00:00
Time | Talk | Presenter |
---|---|---|
12:00 | Embedding status ( 00:15 ) 0 files | Andrew Rose (LBNL) |
12:15 | Production status ( 00:10 ) 0 files | Lidia Didenko (BNL) |
12:25 | imulation geometry for inner tracker R&D, convergence? ( 00:10 ) 0 files | Maxim Potekhin (BNL) |
12:35 | Code changes for inner tracker R&D, other changes ... ( 00:10 ) 0 files | Yuri Fisyak (BNL) |
12:45 | AOB ( 00:10 ) 0 files | All (All) |
Software and Computing phone meeting
, at 00:00 (GMT), duration : 00:00
Time | Talk | Presenter |
---|---|---|
12:00 | SL06d library readiness and main changes ( 00:10 ) 0 files | Lidia Didenko (BNL) |
12:10 | Overview of reconstruction changes in SL06d ( 00:10 ) 0 files | Yuri Fisyak (BNL) |
12:20 | Cu+Cu SVT/SSD review data samples QA ( 00:10 ) 0 files | Christine Nattrass (Yale) |
12:45 | p+p production times ( 00:10 ) 0 files | Jerome Lauret (BNL) |
12:55 | AOB ( 00:05 ) 0 files | All (All) |
13:00 | P06 calibration view, sDCA ( 00:10 ) 0 files | Gene Van Buren (BNL) |
Software and Computing phone meeting
, at 00:00 (GMT), duration : 00:00
Time | Talk | Presenter |
---|---|---|
12:00 | Simulation recent developments ( 00:15 ) 0 files | Maxim Potekhin (BNL) |
12:15 | SSD embedding, progress report ( 00:15 ) 1 file | Jonathan Bouchet (Subatech) |
12:30 | Production status for QM06, status ( 00:10 ) 0 files | Lidia Didenko (BNL) |
12:40 | Xrootd status, activities and remaining problems ( 00:10 ) 1 file | Pavel Jakl (NPI-AS) |
12:50 | AOB ( 00:10 ) 0 files | All (All) |
Software and Computing phone meeting
, at 00:00 (GMT), duration : 00:00
Time | Talk | Presenter |
---|---|---|
12:00 | News from the front ( 00:15 ) 0 files | Chuck Whitten (UCLA) |
12:15 | Simulation for the SVT review ( 00:10 ) 0 files | Maxim Potekhin (BNL) |
12:25 | Library stability ( 00:10 ) 0 files | Lidia Didenko (BNL) |
12:35 | AOB ( 00:10 ) 0 files | All |
Software and Computing phone meeting
, at 00:00 (GMT), duration : 00:00
Time | Talk | Presenter |
---|---|---|
12:00 | News from the front ( 00:10 ) 0 files | Chuck Whitten (UCLA) |
12:10 | Cu+Cu production, timeline and samples overview ( 00:10 ) 0 files | Lidia Didenko (BNL) |
12:20 | Opened discussion ( 00:10 ) 0 files | All |
12:30 | TPC Twist calibration progress ( 00:10 ) 0 files | Eric Hjort (LBNL) |
12:40 | GridLeak distortion progress ( 00:10 ) 0 files | Gene Van Buren (BNL) |
12:50 | Simulation request for SPin ( 00:10 ) 0 files | Maxim Potekhin (BNL) |
Software and Computing phone meeting
, at 00:00 (GMT), duration : 00:00
Time | Talk | Presenter |
---|---|---|
12:00 | SVT Embedding readiness overview ( 00:15 ) 1 file | Helen Caines (Yale) |
12:15 | SSD simulation software chain status, embeding perspectives ( 00:15 ) 1 file | Jonathan Bouchet (Subatech) |
12:30 | Strangeness PWG perspective of the includion of SVT/SSD ( 00:15 ) 0 files | Christine Nattrass (Yale) |
12:45 | HighPt PWG perspectives ( 00:10 ) 0 files | Marco van Leeuwen (LBNL) |
12:55 | AOB ( 00:05 ) 0 files | All (All) |
Software and Computing phone meeting
, at 00:00 (GMT), duration : 00:00
Time | Talk | Presenter |
---|---|---|
12:00 | Year6 p+p (TPC) calibration status ( 00:10 ) 0 files | Gene Van Buren (BNL) |
12:10 | Cu+Cu 200 GeV possible issues ( 00:10 ) 0 files | Yuri Fisyak (BNL) |
12:20 | Simulation, new SVT review request ( 00:10 ) 0 files | Maxim Potekhin (BNL) |
12:30 | Xrootd status and recent developments ( 00:10 ) 1 file | Pavel Jakl (NPI-AS) |
12:50 | AOB ( 00:10 ) 0 files | All (All) |
13:00 | Database load balancer, status and next step ( 00:10 ) 1 file | Mike DePhillips (BNL) |